Abstract: A DC-DC switching converter includes power switches selectively coupling an output terminal with a first voltage or with a second voltage. A driver stage is coupled with the power switches for driving the power switches. A driver control stage is coupled with the driver stage for controlling the operation of the driver stage. An output current sensing circuit is coupled with the output terminal and with the driver control stage, and is configured to sense a sign of an output current delivered by the DC-DC switching converter at the output terminal and to generate control signals for the driver control stage. The driver control stage controls the operation of the driver stage according to states of the control signals received from the output current sensing circuit, for selectively delaying the activation of the power switches depending on the sensed sign of the output current.

Abstract: In an embodiment, a switching converter includes: a switching stage including first and second switching devices for receiving an input voltage and for providing an output voltage; a driving stage including first and second driving devices for driving the first and second switching devices, respectively; a current sensing arrangement for sensing an output current provided by the switching stage; a voltage generation arrangement configured to generate a supply voltage for powering the driving stage, the voltage generation arrangement being configured to adjust the supply voltage according to the sensed output current; and a charge recovery stage configured to store a first electric charge being lost from the first driving device during driving of the first switching device and to release at least partially the stored first electric charge to the second driving device during driving of the second switching device.

Abstract: A direct current (DC) to DC (DC-DC) converter includes a comparator configured to set a pulse width of a signal pulse, the pulse width corresponding to a voltage level of an output voltage of the DC-DC converter; a digital delay line (DDL) operatively coupled to the comparator, the DDL configured increase the pulse width of the signal pulse by linearly introducing delays to the signal pulse; a multiplexer operatively coupled to the DDL, the multiplexer configured to selectively output a delayed version of the signal pulse; and a logic control circuit operatively coupled to the multiplexer and the DDL, the logic control circuit configured to adaptively adjust a precision of the DC-DC converter in accordance with a duty cycle of the DC-DC converter and a setpoint of the DC-DC converter.

Abstract: In an embodiment a DC-DC switching power converter includes a switching circuitry including switches, the switching circuitry configured to receive a DC input voltage and generate a DC output voltage via switching the switches, a switching control circuitry configured to control switching of the switches with a switching signal having a corresponding switching frequency with a corresponding duty cycle, the DC output voltage generated by the switching circuitry depending on the duty cycle, wherein the switching control circuitry is configured to set the duty cycle based on a difference between the DC output voltage and a reference voltage in a closed loop configuration and a compensation network configured to provide stability to an operation of the DC-DC switching power converter, wherein the compensation network has a capacitance having a value depending on the switching frequency.

Abstract: A direct current (DC) to DC (DC-DC) converter includes a comparator setting a pulse width of a signal pulse, the pulse width corresponding to a voltage level of an output voltage of the DC-DC converter; a digital delay line (DDL) operatively coupled to the comparator, the DDL adjusting the pulse width of the signal pulse by linearly introducing delays to the signal pulse; a multiplexer operatively coupled to the DDL, the multiplexer selectively outputting a delayed version of the signal pulse; a phase detector operatively coupled to a system clock and the multiplexer, the phase detector generating a phase error between an output of the multiplexer and the system clock; and a logic control circuit operatively coupled to the multiplexer and the DDL, the logic control circuit adjusting the delay introduced to the signal pulse in accordance with the phase error.

Abstract: A circuit receives an input signal having a first level and a second level. A logic circuit includes a finite state machine circuit, an edge detector circuit, and a timer circuit. The finite state machine circuit is configured to set a mode of operation of the circuit. The edge detector circuit is configured to detect a transition between the first and second level. The timer circuit is configured to determine whether the first or second level is maintained over an interval, which starts from a transition detected by the edge detector circuit. The finite state machine circuit is configured to change the mode of operation based on the timer circuit determining that the first or second level has been maintained over the interval.

Abstract: A direct current (DC) to DC (DC-DC) converter includes a comparator configured to set a pulse width of a signal pulse, the pulse width corresponding to a voltage level of an output voltage of the DC-DC converter; a digital delay line (DDL) operatively coupled to the comparator, the DDL configured increase the pulse width of the signal pulse by linearly introducing delays to the signal pulse; a multiplexer operatively coupled to the DDL, the multiplexer configured to selectively output a delayed version of the signal pulse; and a logic control circuit operatively coupled to the multiplexer and the DDL, the logic control circuit configured to adaptively adjust a precision of the DC-DC converter in accordance with a duty cycle of the DC-DC converter and a setpoint of the DC-DC converter.

Abstract: A direct current (DC) to DC (DC-DC) converter includes a comparator setting a pulse width of a signal pulse, the pulse width corresponding to a voltage level of an output voltage of the DC-DC converter; a digital delay line (DDL) operatively coupled to the comparator, the DDL adjusting the pulse width of the signal pulse by linearly introducing delays to the signal pulse; a multiplexer operatively coupled to the DDL, the multiplexer selectively outputting a delayed version of the signal pulse; a phase detector operatively coupled to a system clock and the multiplexer, the phase detector generating a phase error between an output of the multiplexer and the system clock; and a logic control circuit operatively coupled to the multiplexer and the DDL, the logic control circuit adjusting the delay introduced to the signal pulse in accordance with the phase error.

Abstract: In an embodiment a DC-DC switching power converter includes a switching circuitry including switches, the switching circuitry configured to receive a DC input voltage and generate a DC output voltage via switching the switches, a switching control circuitry configured to control switching of the switches with a switching signal having a corresponding switching frequency with a corresponding duty cycle, the DC output voltage generated by the switching circuitry depending on the duty cycle, wherein the switching control circuitry is configured to set the duty cycle based on a difference between the DC output voltage and a reference voltage in a closed loop configuration and a compensation network configured to provide stability to an operation of the DC-DC switching power converter, wherein the compensation network has a capacitance having a value depending on the switching frequency.

Abstract: A DC-DC switching converter includes power switches selectively coupling an output terminal with a first voltage or with a second voltage. A driver stage is coupled with the power switches for driving the power switches. A driver control stage is coupled with the driver stage for controlling the operation of the driver stage. An output current sensing circuit is coupled with the output terminal and with the driver control stage, and is configured to sense a sign of an output current delivered by the DC-DC switching converter at the output terminal and to generate control signals for the driver control stage. The driver control stage controls the operation of the driver stage according to states of the control signals received from the output current sensing circuit, for selectively delaying the activation of the power switches depending on the sensed sign of the output current.

Abstract: In an embodiment, a switching converter includes: a switching stage including first and second switching devices for receiving an input voltage and for providing an output voltage; a driving stage including first and second driving devices for driving the first and second switching devices, respectively; a current sensing arrangement for sensing an output current provided by the switching stage; a voltage generation arrangement configured to generate a supply voltage for powering the driving stage, the voltage generation arrangement being configured to adjust the supply voltage according to the sensed output current; and a charge recovery stage configured to store a first electric charge being lost from the first driving device during driving of the first switching device and to release at least partially the stored first electric charge to the second driving device during driving of the second switching device.

Abstract: In an embodiment, a switching converter includes: a switching stage configured to receive a direct current input voltage, receive a driving signal for driving the switching stage, and provide a direct current output voltage according to the input voltage and the driving signal; a driving stage configured to provide the driving signal to the switching stage; a current sensing circuit configure to sense an output current provided by the switching stage; and a voltage generation circuit configured to generate at least one supply voltage for powering the driving stage, and adjust the at least one supply voltage according to the output current.

Abstract: A circuit receives an input signal having a first level and a second level. A logic circuit includes a finite state machine circuit, an edge detector circuit, and a timer circuit. The finite state machine circuit is configured to set a mode of operation of the circuit. The edge detector circuit is configured to detect a transition between the first and second level. The timer circuit is configured to determine whether the first or second level is maintained over an interval, which starts from a transition detected by the edge detector circuit. The finite state machine circuit is configured to change the mode of operation based on the timer circuit determining that the first or second level has been maintained over the interval.

Abstract: Switching circuitry includes first and second transistors in series between two terminals and including a common control node with a capacitance between the common control node and an intermediate point. A control circuit includes first and second circuits configured to charge and discharge the capacitance as a function of first and second control signals. The control circuit includes a third circuit having a plurality of diodes and a switch that operates when the voltage at the capacitance is greater than a threshold two diodes in cascade between the intermediate point and the common control node to enable current flow from the intermediate point to the common control node. When the voltage at the capacitance is smaller than the given threshold two diodes are connected in series between the common control node and the intermediate point to enable current flow from the common control node to the intermediate point.

Abstract: A gate driver circuit for a half bridge or full bridge output driver stage having a high side branch connected to one or more high side transistors and a low side branch connected to one or more low side transistors. A high side gate driver and a low side gate driver receive input signals at a low voltage level and output signals at a high voltage level as gate driving signals for the high side transistors and low side transistors. Each of the high side and the low side branches of the gate driver includes a set-reset latch having a signal output that is fed as a gate signal to the corresponding transistor of the half bridge or full bridge driver. A differential capacitive level shifter circuit receives the input signals at a low voltage level and outputs high voltage signals to drive the set and reset inputs of the set-reset latch.

Abstract: Switching circuitry includes first and second transistors in series between two terminals and including a common control node with a capacitance between the common control node and an intermediate point. A control circuit includes first and second circuits configured to charge and discharge the capacitance as a function of first and second control signals. The control circuit includes a third circuit having a plurality of diodes and a switch that operates when the voltage at the capacitance is greater than a threshold two diodes in cascade between the intermediate point and the common control node to enable current flow from the intermediate point to the common control node. When the voltage at the capacitance is smaller than the given threshold two diodes are connected in series between the common control node and the intermediate point to enable current flow from the common control node to the intermediate point.

Abstract: A gate driver circuit for a half bridge or full bridge output driver stage having a high side branch connected to one or more high side transistors and a low side branch connected to one or more low side transistors. A high side gate driver and a low side gate driver receive input signals at a low voltage level and output signals at a high voltage level as gate driving signals for the high side transistors and low side transistors. Each of the high side and the low side branches of the gate driver includes a set-reset latch having a signal output that is fed as a gate signal to the corresponding transistor of the half bridge or full bridge driver. A differential capacitive level shifter circuit receives the input signals at a low voltage level and outputs high voltage signals to drive the set and reset inputs of the set-reset latch.

Abstract: An energy-harvesting system includes a transducer to convert environmental energy into a harvesting electrical signal. A storage element stores electrical energy derived from conversion of the harvested environmental energy. A harvesting interface supplies an electrical charging signal to the storage element. The harvesting interface is selectively connected to the storage element in response to a control signal. The control signal causes the connection when the harvesting electrical signal exceeds a threshold. Conversely, the control signal causes the disconnection when the harvesting electrical signal is less than the threshold.

Abstract: The operation of a circuit exhibiting a delay that is subject to a time spread as a function of process, voltage, and temperature variations is synchronized with a synchronization signal. A digital delay corresponding to the time spread is applied to the synchronization signal. The digital delay is generated via cascaded delay elements having respective delay values and by controlling the number of cascaded delay elements in the circuit that are applied to the synchronization signal.

Abstract: The operation of a circuit exhibiting a delay that is subject to a time spread as a function of process, voltage, and temperature variations is synchronized with a sync signal by applying to the sync signal a digital delay, which can add to the delay that is subject to time spread. The digital delay is generated via cascaded delay elements having respective delay values and by controlling the number of cascaded delay elements in the circuit.