Patents by Inventor Valeria Puglisi

Valeria Puglisi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230170271
    Abstract: An electronic device, comprising: a semiconductor body of silicon carbide; an insulating layer on a surface of the semiconductor body; a layer of metal material extending in part on the surface of the semiconductor body and in part on the insulating layer; a SiN interface layer on the layer of metal material and the insulating layer; a passivation layer on the interface layer; and an anchoring element that protrudes from the passivation layer towards the first insulating layer and extends in the first insulating layer underneath the interface layer.
    Type: Application
    Filed: November 16, 2022
    Publication date: June 1, 2023
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Valeria PUGLISI, Gabriele BELLOCCHI, Simone RASCUNA'
  • Publication number: 20230170390
    Abstract: An electronic device comprising: a semiconductor body of silicon carbide; a first insulating layer on a first surface of the semiconductor body, of a first material with electrical-insulator or dielectric characteristics; a first layer of metal material extending in part on the first surface of the semiconductor body and in part on the first insulating layer; an interface layer on the first layer of metal material and on the first insulating layer, of a second material different from the first material; and a passivation layer of the first material on the interface layer. The first material is silicon oxide, and the second material is silicon nitride.
    Type: Application
    Filed: September 9, 2022
    Publication date: June 1, 2023
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Simone RASCUNA', Valeria PUGLISI, Gabriele BELLOCCHI
  • Patent number: 9024357
    Abstract: A method for manufacturing a HEMT transistor includes: realizing an undoped epitaxial layer on a substrate; realizing a barrier epitaxial layer on the undoped epitaxial layer so as to form a heterojunction; realizing source and drain structures, separated from one other, on the barrier epitaxial layer; depositing an insulating layer on the barrier epitaxial layer and on the source and drain structures; and photolithographic defining the insulating layer, defining first and second insulating portions in correspondence of the source and drain structures, respectively, and exposing a portion of the barrier epitaxial layer. The method further comprises: forming first and second spacers lying at the corners of the first and second insulating portions; and depositing a gate metal structure at least partially covering said first and second insulating portions, and said first and second spacers, said gate metal structure being a field plate of the HEMT transistor.
    Type: Grant
    Filed: April 6, 2012
    Date of Patent: May 5, 2015
    Assignee: STMicroelectronics S.r.l.
    Inventors: Valeria Puglisi, Corinna Altamore, Giovanni Abagnale
  • Publication number: 20120261720
    Abstract: A method for manufacturing a HEMT transistor includes: realizing an undoped epitaxial layer on a substrate; realizing a barrier epitaxial layer on the undoped epitaxial layer so as to form a heterojunction; realizing source and drain structures, separated from one other, on the barrier epitaxial layer; depositing an insulating layer on the barrier epitaxial layer and on the source and drain structures; and photolithographic defining the insulating layer, defining first and second insulating portions in correspondence of the source and drain structures, respectively, and exposing a portion of the barrier epitaxial layer. The method further comprises: forming first and second spacers lying at the corners of the first and second insulating portions; and depositing a gate metal structure at least partially covering said first and second insulating portions, and said first and second spacers, said gate metal structure being a field plate of the HEMT transistor.
    Type: Application
    Filed: April 6, 2012
    Publication date: October 18, 2012
    Applicant: STMicroelectronics S.r.I.
    Inventors: Valeria Puglisi, Corinna Altamore, Giovanni Abagnale