Abstract: The present disclosure relates to a structure including a memory built-in self test (MBIST) circuit which is configured to repair a multi-cell failure for a plurality of patterns in a single wordline of a sliding window of a memory.

Abstract: The present disclosure relates to a structure including a memory built-in self test (MBIST) circuit which is configured to repair a multi-cell failure for a plurality of patterns in a single wordline of a sliding window of a memory.

Abstract: A built-in self-test (BIST) system comprising repair logic structured to share state logic of failed memories across local registers located in a shared registry which services multiple memories, wherein each of the local registers is associated with a different memory.

Abstract: A built-in self-test (BIST) system comprising repair logic structured to share state logic of failed memories across local registers located in a shared registry which services multiple memories, wherein each of the local registers is associated with a different memory.

Abstract: Each register in each built-in self-test (BIST) controller contains a BIST controller-specific start count value that is different from at least one other BIST controller-specific start count. A test controller provides a start command simultaneously to all the BIST controllers. This causes each of the BIST controllers to simultaneously begin a countdown of the BIST controller-specific start count values, using a counter. Each of the BIST controllers starts a test procedure in a corresponding BIST domain when the countdown completes (in the corresponding BIST controller). Thus, the test procedure starts at different times in at least two of the BIST domains based on the difference of the BIST controller-specific start count values in the different registers. Further, during the test procedure, each stagger controller can stagger the start of each BIST engine within the corresponding BIST domain to which the stagger controller is connected.

Abstract: A circuit and method of testing a memory and calculating a repair solution for a given address location includes pausing a built in self test (BIST) operation on detection of a failing memory output data of an integrated circuit. During the pause, the circuit and method analyzes “n” number of groups of the failing memory output data during “n” cycles using analysis logic and calculating a repair solution. Normal operations can be resumed.

Abstract: A circuit and method of testing a memory and calculating a repair solution for a given address location includes pausing a built in self test (BIST) operation on detection of a failing memory output data of an integrated circuit. During the pause, the circuit and method analyzes “n” number of groups of the failing memory output data during “n” cycles using analysis logic and calculating a repair solution. Normal operations can be resumed.

Abstract: A circuit and method of testing a memory and calculating a repair solution for a given address location includes pausing a built in self test (BIST) operation on detection of a failing memory output data of an integrated circuit. During the pause, the circuit and method analyzes “n” number of groups of the failing memory output data during “n” cycles using analysis logic and calculating a repair solution. Normal operations can be resumed.

Abstract: In one embodiment, the invention is a method, apparatus, and design structure for built-in self-test for embedded memory in integrated circuit chips. One embodiment of a method for built-in self-test of an embedded memory includes setting up a plurality of test patterns at a speed of a test clock, where the speed of the test clock is slow enough for a tester to directly communicate with a chip in which the memory is embedded, and where the setting up includes loading a plurality of signal states used to communicate the test patterns to one or more components of a built-in self-test system, applying the test patterns to the embedded memory as a microburst at-speed, capturing output data from the embedded memory at-speed, the output data corresponding to only one of test patterns, and comparing the output data to expected data at the speed of the test clock.

Abstract: A method for testing integrated circuits (ICs) by automatically extending addressing for shared array built-in self-test (BIST) circuitry, includes polling a plurality of memories to determine which of the plurality of memories are sharing a first comparison tree and mapping a shared array BIST address space to each of the plurality of memories using the first comparison tree. Additionally, the method includes estimating a shared array BIST completion time corresponding to a most significant bits of a maximum total memory address size under test, reconfiguring the shared array BIST circuitry to accommodate the estimated shared array BIST completion time and testing the plurality of memories sharing the first comparison tree.

Abstract: A method for testing integrated circuits (ICs) by automatically extending addressing for shared array built-in self-test (BIST) circuitry, includes polling a plurality of memories to determine which of the plurality of memories are sharing a first comparison tree and mapping a shared array BIST address space to each of the plurality of memories using the first comparison tree. Additionally, the method includes estimating a shared array BIST completion time corresponding to a most significant bits of a maximum total memory address size under test, reconfiguring the shared array BIST circuitry to accommodate the estimated shared array BIST completion time and testing the plurality of memories sharing the first comparison tree.

Abstract: A system and method for enabling a programmed phase change in a servo track writer (STW) clock providing signals for writing information to a servo track, the phase change programmed to occur in one or more large or small phase bumps in either positive and negative directions, whereby a large phase jump is defined as the largest block of bit unit that can be handled without introducing noise into the system, and a smaller phase bump that is the smallest incremental bit unit that may be programmed to change the servo write clock phase until a final phase offset is reached.

Abstract: A system and method for enabling a programmed phase change in a servo track writer (STW) clock providing signals for writing information to a servo track, the phase change programmed to occur in one or more large or small phase bumps in either positive and negative directions, whereby a large phase jump is defined as the largest block of bit unit that can be handled without introducing noise into the system, and a smaller phase bump that is the smallest incremental bit unit that may be programmed to change the servo write clock phase until a final phase offset is reached.