Abstract: A method of representing a first end-user license agreement (EULA) offered to a user and automatically responding to a subsequent EULA offered to the user is disclosed. The representation may be in a logical language having parameters corresponding to legal terms of the EULA, logical operators, and the capability to form and nest logical expressions. A logical library may store parameters corresponding to legal terms. A logical expression may be created that corresponds to a user's term preferences, and may be evaluated using the terms of a subsequent EULA to automatically determine the user's acceptance or rejection of the subsequent EULA. A user's application preferences of the logical expressions and terms may be received and used by the method. EULA responses may be signified in a log and/or by sending a record or message to the offering party. A similar method is disclosed for other types of electronic agreements.

Abstract: A computer being controlled is coupled via a communications bus to at least one other device comprising one or more authorized management devices. The one or more authorized management devices are coupled to a management port. Only management commands received from authorized management devices via the management port may be executed or otherwise responded to. Management commands received from other devices are ignored. In a preferred embodiment, the communication bus is an IEEE 1394 serial bus. In this manner, the present invention provides for the use of more direct communication technologies, such as the IEEE 394 serial bus, while simultaneously providing a greater degree of security than previously available.

Abstract: Cooperatively scheduling hardware resources by providing information on shared resources within processor packages to the operating system. Logical processors may be included in packages in which some or all processor execution resources are shared among logical processors. In order to better schedule thread execution, information regarding which logical processors are sharing processor execution resources and information regarding which system resources are shared among processor packages is provided to the operating system. Extensions to the SRAT (static resource affinity table) can be used to provide this information.

Abstract: A mechanism whereby a set of microprocessors may be set to a common mode in which the microprocessors utilize one or more features that are common to all microprocessors. The common mode facilitates proper multiprocessor operation and permits a fix (e.g., a microcode patch) to be applied to each of the microprocessors based on this common mode. More particularly, at system startup, firmware or software can detect whether microprocessors are set to run in different modes (e.g., steppings) in a multiprocessor system. If not, the microprocessors are allowed to run in their normal mode, such as by writing a particular value (e.g., zero) to a configuration register associated with each microprocessor. If features are mixed, a different value can be written, (e.g., one), which tells each microprocessor to revert to a common mode of operation for that family of microprocessors, such as corresponding to a common stepping and/or clock speed. A common set of microcode patches may be downloaded to the microprocessors.

Abstract: A set of microprocessors may be set to a common mode in which the microprocessors utilize features that are common to all microprocessors. The common mode facilitates proper multiprocessor operation and permits a fix to be applied to each of the microprocessors based on this common mode. Firmware or software can detect whether microprocessors are set to run in different modes in a multiprocessor system. If not, the microprocessors are allowed to run in their normal mode, such as by writing a value to a configuration register associated with each microprocessor. If features are mixed, a different value can be written which tells each microprocessor to revert to a common mode of operation for that family of microprocessors. A common set of microcode patches may be downloaded to the microprocessors. Alternatively, the various microprocessors may also be instructed to run in a particular mode that emulates a particular stepping.

Abstract: Cooperatively scheduling hardware resources by providing information on shared resources within processor packages to the operating system. Logical processors may be included in packages in which some or all processor execution resources are shared among logical processors. In order to better schedule thread execution, information regarding which logical processors are sharing processor execution resources and information regarding which system resources are shared among processor packages is provided to the operating system. Extensions to the SRAT (static resource affinity table) can be used to provide this information.