Patents by Inventor Valerie Ward

Valerie Ward has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11034980
    Abstract: Disclosed herein are engineered cells and cell-free systems, compositions, and methods for conversion of isopentenols to isoprenoid precursors.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: June 15, 2021
    Assignee: Massachusetts Institute of Technology
    Inventors: Steven McBride Edgar, Alkiviadis Orfefs Chatzivasileiou, Valerie Ward, Gregory Stephanopoulos
  • Publication number: 20190367950
    Abstract: Disclosed herein are engineered cells and cell-free systems, compositions, and methods for conversion of isopentenols to isoprenoid precursors.
    Type: Application
    Filed: May 29, 2019
    Publication date: December 5, 2019
    Applicant: Massachusetts Institute of Technology
    Inventors: Steven McBride Edgar, Alkiviadis Orfefs Chatzivasileiou, Valerie Ward, Gregory Stephanopoulos
  • Patent number: 6555896
    Abstract: A etch stop layer for use in a silicon oxide dry fluorine etch process is made of silicon nitride with hydrogen incorporated in it either in the form of N—H bonds, Si—H bonds, or entrapped free hydrogen. The etch stop layer is made by either increasing the NH3 flow, decreasing the SiH4 flow, decreasing the nitrogen flow, or all three, in a standard PECVD silicon nitride fabrication process. The etch stop can alternatively be made by pulsing the RF field in either a PECVD process or an LPCVD process.
    Type: Grant
    Filed: December 21, 2000
    Date of Patent: April 29, 2003
    Assignee: Micron Technology, Inc.
    Inventors: David A. Cathey, J. Brett Rolfson, Valerie A. Ward, Karen M. Winchester
  • Publication number: 20010003679
    Abstract: A etch stop layer for use in a silicon oxide dry fluorine etch process is made of silicon nitride with hydrogen incorporated in it either in the form of N—H bonds, O—H bonds, or entrapped free hydrogen. The etch stop layer is made by either increasing the NH3 flow, decreasing the SiH4 flow, decreasing the nitrogen flow, or all three, in a standard PECVD silicon nitride fabrication process. The etch stop can alternatively be made by pulsing the RF field in either a PECVD process or an LPCVD process.
    Type: Application
    Filed: December 21, 2000
    Publication date: June 14, 2001
    Inventors: David A. Cathey, J. Brett Rolfson, Valerie A. Ward, Karen M. Winchester
  • Patent number: 6232218
    Abstract: A etch stop layer for use in a silicon oxide dry fluorine etch process is made of silicon nitride with hydrogen incorporated in it either in the form of N—H bonds, O—H bonds, or entrapped free hydrogen. The etch stop layer is made by either increasing the NH3 flow, decreasing the SiH4 flow, decreasing the nitrogen flow, or all three, in a standard PECVD silicon nitride fabrication process. The etch stop can alternatively be made by pulsing the RF field in either a PECVD process or an LPCVD process.
    Type: Grant
    Filed: August 19, 1999
    Date of Patent: May 15, 2001
    Assignee: Micron Technology, Inc.
    Inventors: David A. Cathey, J. Brett Rolfson, Valerie A. Ward, Karen M. Winchester
  • Patent number: 6222257
    Abstract: A etch stop layer for use in a silicon oxide dry fluorine etch process is made of silicon nitride with hydrogen incorporated in it either in the form of N—H bonds, Si—H bonds, or entrapped free hydrogen. The etch stop layer is made by either increasing the NH3 flow, decreasing the SiH4 flow, decreasing the nitrogen flow, or all three, in a standard PECVD silicon nitride fabrication process. The etch stop can alternatively be made by pulsing the RF field in either a PECVD process or an LPCVD process.
    Type: Grant
    Filed: August 6, 1999
    Date of Patent: April 24, 2001
    Assignee: Micron Technology, Inc.
    Inventors: David A. Cathey, J. Brett Rolfson, Valerie A. Ward, Karen M. Winchester
  • Patent number: 6013943
    Abstract: A etch stop layer for use in a silicon oxide dry fluorine etch process is made of silicon nitride with hydrogen incorporated in it either in the form of N--H bonds, O--H bonds, or entrapped free hydrogen. The etch stop layer is made by either increasing the NH.sub.3 flow, decreasing the SiH.sub.4 flow, decreasing the nitrogen flow, or all three, in a standard PECVD silicon nitride fabrication process. The etch stop can alternatively be made by pulsing the RF field in either a PECVD process or an LPCVD process.
    Type: Grant
    Filed: May 5, 1997
    Date of Patent: January 11, 2000
    Assignee: Micron Technology, Inc.
    Inventors: David A. Cathey, J. Brett Rolfson, Valerie A. Ward, Karen M. Winchester
  • Patent number: 6004875
    Abstract: A etch stop layer for use in a silicon oxide dry fluorine etch process is made of silicon nitride with hydrogen incorporated in it either in the form of N--H bonds, O--H bonds, or entrapped free hydrogen. The etch stop layer is made by either increasing the NH.sub.3 flow, decreasing the SiH.sub.4 flow, decreasing the nitrogen flow, or all three, in a standard PECVD silicon nitride fabrication process. The etch stop can alternatively be made by pulsing the RF field in either a PECVD process or an LPCVD process.
    Type: Grant
    Filed: November 15, 1995
    Date of Patent: December 21, 1999
    Assignee: Micron Technology, Inc.
    Inventors: David A. Cathey, J. Brett Rolfson, Valerie A. Ward, Karen M. Winchester
  • Patent number: 5449314
    Abstract: A method of forming a planarized dielectric layer includes depositing a dielectric material on a substrate with a dopant concentration that decreases with depth and then chemically mechanically polishing the doped dielectric material. During the chemical mechanical polishing process the polish rate will be relatively fast initially but will slow down as the lighter doped material is contacted. Global planarity and polish selectivity are improved because the dopant gradient will automatically slow down the polish rate in areas where the lighter doped material is contacted. The high points of the dielectric material will thus polish faster than the low points. In an alternate embodiment of the invention, an underlying layer is deposited below a dopant graded dielectric layer having a predetermined dopant concentration that decreases with depth. The underlying layer may be undoped or uniformly doped.
    Type: Grant
    Filed: April 25, 1994
    Date of Patent: September 12, 1995
    Assignee: Micron Technology, Inc.
    Inventors: Scott Meikle, Valerie Ward