Abstract: A method of manufacturing a semiconductor virtual ground memory device having a matrix of floating gate memory cells formed on a semiconductor substrate with a plurality of continuous bit lines extending across the substrate as discrete parallel stripes. The device also includes a circuit portion for selection transistors and decode and address circuit portions having P-channel and N-channel MOS transistors. According to the method, N-wells are formed in at least one substrate portion to accommodate the P-channel transistors, active areas of all transistors are defined using a screening mask, and then an isolation layer is grown through the apertures of the screening mask. The screening mask is not open over the matrix region of the memory cells.

Abstract: A method is provided of manufacturing a P-channel native MOS transistor in a circuit integrated on a semiconductor which also includes a matrix of non-volatile memory cells of the floating gate type with two polysilicon levels having an interpoly dielectric layer sandwiched between the two polysilicon levels. The method has the following steps: (1) masking and defining active areas of the discrete integrated devices; (2) masking and defining the first polysilicon level using a Poly1 mask; and (3) masking and defining an intermediate dielectric layer using a matrix mask. The length of the native threshold channel of the native transistor is defined by means of the matrix mask and by etching away the interpoly dielectric layer.