Abstract: A control method and system to control a pair of electric motors driving a vehicle. The steps provided for are: determining, in a control cycle N and by means of a first processing core, for a first electric motor, a first electric current target based on a first torque or speed target; determining, in the control cycle N and by means of a second processing core, for a second electric motor, a second electric current target based on a second torque or speed target; controlling, in the control cycle N and by means of the first processing core, a first electronic power converter connected to the first electric motor so as to pursue the first electric current target; and controlling, in the control cycle N and by means of the second processing core, a second electronic power converter connected to the second electric motor so as to pursue the second electric current target.

Abstract: A control method and system to control a pair of electric motors driving a vehicle. The steps provided for are: determining, in a control cycle N and by means of a first processing core, for a first electric motor, a first electric current target based on a first torque or speed target; determining, in the control cycle N and by means of a second processing core, for a second electric motor, a second electric current target based on a second torque or speed target; controlling, in the control cycle N and by means of the first processing core, a first electronic power converter connected to the first electric motor so as to pursue the first electric current target; and controlling, in the control cycle N and by means of the second processing core, a second electronic power converter connected to the second electric motor so as to pursue the second electric current target.

Abstract: A system for diagnosing a driver and detecting circuit anomalies therein includes: voltage comparator circuits for generating diagnostic logic signals, each of which indicates the existence of a corresponding type of anomaly; and a coding circuit to receive the diagnostic logic signals and to output information relating to an overall operating state of the driver. The coding circuit includes a first portion to provide at its output first logic input signals indicating the last anomaly to occur since a system reset operation. The coding circuit also includes a second portion for coding the first logic input signals. The second portion includes a sequential logic network to receive the first logic input signals and at least one second logic signal indicating the current operating phase of the driver. The second portion provides, as a function of the first and second logic signals, a stable internal state to determine the output information in the form of an N bit coded word.

Abstract: A circuit comprises a measurement resistor in series with a heater, a detector circuit for providing a signal indicative of the current flowing in the resistor, switching devices for controlling the connection of the heater to a voltage source and the connection of the measurement resistor in the supply circuit comprising the source and the heater, and a control unit arranged to drive the switching devices in a manner such that each time the heater is activated, the measurement resistor is kept disconnected from the supply circuit of the heater for a predetermined period of time and the measurement resistor is then connected in the supply circuit of the heater.

Abstract: The circuit includes sensors for supplying electrical signals indicative of the current flowing in the field winding of the generator in operation and a control circuit operatively connected to the sensors. The control circuit is arranged to control the transistor which drives the field winding so that the voltage at the battery terminals remains substantially constant with variations in the current supplied to the battery by the generator.

Abstract: The interface circuit described comprises a plurality of control stages, each of which can detect and indicate a short-circuit in the corresponding load or the associated power transistor.In particular, the interface circuit is arranged to disable a transistor permanently when short-circuits occur repeatedly in the load in order to prevent damage to the transistor.

Abstract: The voltage-regulator circuit includes:a driver transistor whose collector-emitter path is in series with the field winding between two poles of a source of a direct-current voltage, anda control circuit adapted to drive the transistor in an on-off manner in dependence on the value assumed by the voltage supplied by the generator in comparison with a reference voltage and in dependence on the field current detected by a resistor connected to the transistor.

Abstract: During the piloting of the load, the current intensity and the voltage present in the load are monitored by the comparison of their values with a current threshold and with a window of permissible voltage values. When the voltage is outside the window of permissible values and/or the current falls below its threshold, a fault message is generated and the nature of the fault (open load, short circuit to earth, short circuit to the supply voltage) is also identified by the emission of a corresponding signal of a diagnostic nature. The identification of the faulty stage or stages is also provided for in the case of a circuit including several stages in parallel.

Abstract: A network for supplying identical biasing voltages and programmable direct currents to a plurality of mutually similar transceivers, connected across respective transmission lines, is integrated with the associated transceivers in a common semiconductor body and comprises a generator of fixed reference voltage determined by the band gap of the semiconductor. The reference voltage is applied in parallel to the bases of several NPN transistors emitting the same biasing voltage as a result thereof. This reference voltage also drives an NPN pilot transistor lying in series with an external resistor through which it draws a small programmed current. Through two cascaded amplification stages formed by NPN transistors operating in the ECL mode, with the second stage designed as a multiple-output current mirror, the programmed current is stepped up to provide the several direct currents required by the associated transceivers.