Patents by Inventor Valerio Lanieri

Valerio Lanieri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240260261
    Abstract: Various implementations described herein are related to a device having a memory architecture with a multi-stack of transistors that may be arranged in a multi-bitcell stack configuration. Also, the memory architecture may have a wordline that may be shared across the transistors of the multi-stack of transistors with each transistor coupled to a different bitline.
    Type: Application
    Filed: January 30, 2023
    Publication date: August 1, 2024
    Inventors: Yannick Marc Nevers, Valerio Lanieri, Amit Chhabra
  • Publication number: 20230335537
    Abstract: Various implementations described herein are related to a device having a multi-transistor structure for use in circuit architecture. The multi-transistor structure may have a multi-transistor stack of at least one of N-type transistors or P-type transistors that are arranged in a multi-device stack configuration. Also, a physical layout of the multi-device stack configuration may provide a common-centroid configuration for process mismatch cancellation in at least one of the X-Y-Z axes.
    Type: Application
    Filed: April 15, 2022
    Publication date: October 19, 2023
    Inventors: Lokesh Kumar Saini, Amit Chhabra, Valerio Lanieri