Abstract: A low-dropout regulator having an output current branch being arranged between a supply line to provide a supply potential and an output node to provide a regulated output voltage. The output current branch includes an output driver to provide an output current at the output node. The output driver has a control connection to apply a control voltage to operate the output driver with a different conductivity in dependence on the control voltage. The LDO includes an input amplifier stage to provide the control voltage to the control connection of the output driver. The input amplifier stage is configured to provide the control voltage with a different slew rate in dependence on an increase or decrease of the output current.

Abstract: A low-dropout regulator comprises an output current branch (10) being arranged between a supply line (Vsupply) to provide a supply potential (VDD) and an output node (O) to provide a regulated output voltage (Vreg). The output current branch (10) comprises an output driver (20) to provide an output current (Iout) at the output node (O). The output driver (20) has a control connection (G20) to apply a control voltage (Vc) to operate the output driver (20) with a different conductivity in dependence on the control voltage (Vc). The LDO comprises an input amplifier stage (30) to provide the control voltage (Vc) to the control connection (G20) of the output driver (20). The input amplifier stage (30) is configured to provide the control voltage (Vc) with a different slew rate in dependence on an increase or decrease of the output current (Iout).

Abstract: The invention relates to a low supply voltage analog multiplier which comprises a pair of differential cells, each cell comprising a pair of bipolar transistors with coupled emitters. A first transistor of each cell receives an input signal on its base terminal and has its collector terminal coupled to a first voltage reference through a bias member. Advantageously, the second transistor of each cell is a diode configuration, and the cells are interconnected at a common node corresponding to the base terminals of the second transistors in each pair. This multiplier can be supplied very low voltages and still exhibit a high rate of operation along with reduced harmonic distortion of the output signal, even with input signals of peak-to-peak amplitude above 600 mV.

Abstract: A finite impulse response (FIR) filter for implementing a Hilbert transform is provided. The FIR filter includes a plurality of programmable delay cells connected in cascade between an input terminal of the FIR filter and an output terminal of the FIR filter. Each programmable delay cell has associated therewith a constant filter coefficient and a programmable delay coefficient. The FIR filter is also applicable for processing signals originated by the reading of data from a magnetic storage media which employs perpendicular recording.

Abstract: A circuit device for restoring the symmetry of an analog signal originated by the reading of data from magnetic supports, including at least one differential cell multiplier whose cell includes a pair of input MOS transistors having respective conduction terminals linked together at a circuit node. Advantageously, provided in parallel with each of the cell input transistors, are a plurality of transistors individually connectable to and disconnectable from each of the input transistors by corresponding switches.

Abstract: This invention relates to a circuit structure of the feedforward type with programmable zeroes, particularly for synthesizing time-continual filters. This structure comprises a pair of amplification cells interconnected at least one interconnection node and connected between a first signal input of a first cell and an output terminal of the second cell, each cell comprising a pair of transistors which have a conduction terminal in common and have the other conduction terminals coupled respectively to a first voltage reference through respective bias members. The structure further comprises a circuit leg connecting a node of the first cell to the output terminal and comprising a transistor which has a control terminal connected to the node of the first cell, a first conduction terminal connected to the output terminal, and a second conduction terminal coupled to a second voltage reference through a capacitor.

Abstract: An elementary cell structure for programmable time-continuous analog filters and in particular for the processing of analog signals in read/write operations on magnetic supports comprises an amplifier stage provided with a pair of structurally identical transconductance half-cells connected together in a common circuit node. With a cascade of cells of this type is provided a time-continuous analog delay line which is used in a transverse time-continuous analog filter. This filter comprises a cascade of identical delay lines connected through multiplier nodes to a final summation node.

Abstract: The invention relates to a low supply voltage analog multiplier which comprises a pair of differential cells, each cell comprising a pair of bipolar transistors with coupled emitters. A first transistor of each cell receives an input signal on its base terminal and has its collector terminal coupled to a first voltage reference through a bias member. Advantageously, the second transistor of each cell is a diode configuration, and the cells are interconnected at a common node corresponding to the base terminals of the second transistors in each pair. This multiplier can be supplied very low voltages and still exhibit a high rate of operation along with reduced harmonic distortion of the output signal, even with input signals of peak-to-peak amplitude above 600 mV.

Abstract: A circuit device for restoring the symmetry of an analog signal originated by the reading of data from magnetic supports, including at least one differential cell multiplier whose cell includes a pair of input MOS transistors having respective conduction terminals linked together at a circuit node. Advantageously, provided in parallel with each of the cell input transistors, are a plurality of transistors individually connectable to and disconnectable from each of the input transistors by corresponding switches.

Abstract: A finite impulse response (FIR) filter for implementing a Hilbert transform is provided. The FIR filter includes a plurality of programmable delay cells connected in cascade between an input terminal of the FIR filter and an output terminal of the FIR filter. Each programmable delay cell has associated therewith a constant filter coefficient and a programmable delay coefficient. The FIR filter is also applicable for processing signals originated by the reading of data from a magnetic storage media which employs perpendicular recording.

Abstract: A waveform track-and-hold circuit receives an analog input signal and generates an analog output signal. The waveform track-and-hold circuit includes a differential separating input stage, a differential separating output stage, first and second charge storage means, and switch means. The first and second charge storage means are coupled between the differential separating input stage and the differential separating output stage, and the switch means are controlled by a logic control signal so as to selectively isolate the first and second charge storage means from the analog input signal. Additionally, the differential separating input stage includes a push-pull input stage connected to the switch means and receiving the analog input signal. In a preferred embodiment, the analog input signal is supplied to the emitters of transistors that form the push-pull input stage, the collectors of the transistors are connected to the switch means, and the transistors are part of current mirror circuits.

Abstract: A programmable-gain multistage amplifier with broad bandwidth and reduced phase variations having a differential input stage biased by a first current source and to which a differential voltage signal is fed, the stage being connected to a pair of diodes in which the cathode terminals are connected to respective bipolar transistors, which are biased by a second current source and in which the collector terminals are connected to load resistors, the differential output of the amplifier being provided at the collector terminals of the bipolar transistors.

Abstract: A device generates pulses of high-precision with programmable duration. The device includes first, second and third pulse generator circuits. The first pulse generator circuit receives at an input a pulse generation command signal, and provides at an output a first pulse for loading the contents of a register in a counter. The second pulse generator circuit is triggered by the first pulse provided by the first pulse generator circuit. The third pulse generator circuit is triggered by a second pulse provided by the second pulse generator circuit, and generates a third pulse to restart the second pulse generator circuit. The second pulse provided by the second pulse generator circuit forms a clock signal for the counter to produce a decrement in the counter. The output signal from the counter is the pulsed signal to be generated. The duration of the pulsed signal is determined by the content of the counter.

Abstract: A feedforward circuit structure with programmable zeros for synthesizing continuous-time filters, delay lines, and the like is described. The circuit comprises a first cell and a second cell which are cascade-connected. Each one of the first and second cells comprises first and second pairs of bipolar transistors. The emitter terminals of the first pair of transistors are connected to a first current source, and the emitter terminals of the second pair of transistors are connected to a second current source. A first high-impedance element is connected between the first and second pairs of transistors, and a second high-impedance element is connected at an output of the second pair of transistors. A fifth transistor is connected between the collector terminal of a first transistor of the first pair of transistors and the collector terminal of a second transistor of the second pair of transistors.

Abstract: The device is to be used with a parallel architecture partial response maximum likelihood (PRML) reading apparatus comprising a variable-gain input amplifier, a low-pass analog filter, a transversal continuous-time analog filter and two distinct and parallel processing channels interposed between the transversal analog filter and an RLL-NRZ decoder. The two processing channels comprise respective analog-digital converters and respective Viterbi detectors and operate according to sampling sequences that alternate with one another. The device for processing the servo signals comprises a rectifier connected to the outputs of the analog-digital converters and an integrator.

Abstract: An amplifier with programmable gain and input linearity at high frequency allows an increase in the gain without effecting input linearity and without significantly increasing current consumption. The amplifier includes an input stage which receives a voltage signal for performing a current conversion thereof with compression. An output stage is connected to the input stage and decompresses the signal provided by the input stage for producing gain amplification thereof. The amplifier further includes at least one current amplifier stage interposed between the input stage and the output stage. The at least one current amplifier includes at least one bipolar transistor series-connected to a load diode and to a current source. A reduction in the transconductance of the load diode is provided in the at least one amplifier stage to determine a programmable gain factor for the amplifier.

Abstract: A low offset amplifier has an output stage constituted by an npn transistor and a pnp transistor in a push-pull arrangement, and a driver stage. The latter includes a current-mirror circuit having, in its input branch, a pnp transistor in series with a first constant-current generator and, in its output branch, an npn transistor, and two complementary bipolar transistors with collectors connected together to the output terminal and the bases are connected together to the input terminal of the amplifier. The emitter of the pnp transistor of the driver stage is connected to the positive terminal of the supply by a second constant-current generator and to the base of the npn transistor of the output stage, and the emitter of the npn transistor of the driver stage is connected to the negative terminal of the supply by the npn transistor of the output branch of the current-mirror circuit and to the base of the pnp transistor of the output stage. The amplifier has a very low or zero offset (Vos=Vout-Vin).

Abstract: A current-controlled multivibrator having increased accuracy independent of variations in process and temperature. The oscillator employs a bandgap voltage in combination with a current generator to ensure operational stability despite temperature and process variations.

Abstract: A BiCMOS transconductor differential stage for high frequency filters includes an input circuit portion having signal inputs and a pair of MOS transistors having their respective gate terminals corresponding to the signal inputs. The differential stage has an output circuit portion having signal outputs and a pair of bipolar transistors connected together with a common base inserted between the inputs and the outputs in a cascode configuration. The differential stage includes a switching device associated with at least one of the bipolar transistors to change the connections between parasitic capacitors present in the differential stage. The switching device also has at least one added bipolar transistor connected in a removable manner in parallel with the corresponding bipolar cascode transistor.

Abstract: The system includes various circuit units each having a capacitor and a charging circuit for defining a quantity depending upon the ratio (I/C) between the charging current and the capacitance of the capacitors. In order to compensate automatically for deviations of the actual capacitances from the nominal capacitances due to fluctuations in the parameters of the integrated-circuit manufacturing process, the system has a phase-locked loop which uses one of the circuit units as an adjustable oscillator, and current transducer means which regulates the charging currents of the capacitors of the circuit units in dependence on the regulated charging current of the capacitor of the oscillator, or the error current of the PLL loop.