Patents by Inventor Valeriy Balabanov

Valeriy Balabanov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of analytical placement with weighted-average wirelength model
    Patent number: 8689164
    Abstract: A computer-implemented method to generate a placement for a plurality of instances for an integrated circuit (IC) by utilizing a novel weighted-average (WA) wirelength model, which outperforms a well-known log-sum-exp wirelength model, to approximate the total wirelength. The placement is determined by performing an optimization process on an objective function which includes a wirelength function approximated by the WA wirelength model. The method can be extended to generate a placement for a plurality of instances for a three-dimensional (3D) integrated circuit (IC) which considers the sizes of through-silicon vias (TSVs) and the physical positions for TSV insertion. With the physical positions of TSVs determined during placement, 3D routing can easily be accomplished with better routed wirelength, TSV counts, and total silicon area.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: April 1, 2014
    Assignee: National Taiwan University
    Inventors: Valeriy Balabanov, Meng-Kai Hsu, Yao-Wen Chang
  • METHOD OF ANALYTICAL PLACEMENT WITH WEIGHTED-AVERAGE WIRELENGTH MODEL
    Publication number: 20130097574
    Abstract: A computer-implemented method to generate a placement for a plurality of instances for an integrated circuit (IC) by utilizing a novel weighted-average (WA) wirelength model, which outperforms a well-known log-sum-exp wirelength model, to approximate the total wirelength. The placement is determined by performing an optimization process on an objective function which includes a wirelength function approximated by the WA wirelength model. The method can be extended to generate a placement for a plurality of instances for a three-dimensional (3D) integrated circuit (IC) which considers the sizes of through-silicon vias (TSVs) and the physical positions for TSV insertion. With the physical positions of TSVs determined during placement, 3D routing can easily be accomplished with better routed wirelength, TSV counts, and total silicon area.
    Type: Application
    Filed: October 18, 2011
    Publication date: April 18, 2013
    Applicant: NATIONAL TAIWAN UNIVERSITY
    Inventors: Valeriy Balabanov, Meng-Kai Hsu, Yao-Wen Chang