Abstract: Aspects of the disclosed technology relate to techniques of full-chip assessment of time-dependent dielectric breakdown. A layout design is analyzed to identify matching patterns that match a pre-calculated pattern in a pattern database. Each of pre-calculated patterns in the pattern database has a time-to-failure characteristic value pre-computed based on a model of electric current path generation and evolution. Time-to-failure characteristic values are then determined for the matching patterns based on the pre-computed time-to-failure characteristic values and electric attributes of geometric elements in each of the matching patterns. Based on the time-to-failure characteristic values, matching patterns most susceptible to time-dependent dielectric breakdown are identified and fixed.

Abstract: Aspects of the disclosed technology relate to techniques of inserting stress-enhancing filler cells for leakage reduction. Stress analysis is first performed to identify devices with large leakage current in a layout design. An optimization zone in a row of cells that contains one or more of the devices with large leakage current is then determined. Stress-enhancing filler cells are inserted into the optimization zone to replace some or all of the one or more filler cells while placement of the cells in the optimization zone is adjusted based on a leakage reduction analysis.

Abstract: Aspects of the disclosed technology relate to techniques of full-chip assessment of time-dependent dielectric breakdown. A layout design is analyzed to identify matching patterns that match a pre-calculated pattern in a pattern database. Each of pre-calculated patterns in the pattern database has a time-to-failure characteristic value pre-computed based on a model of electric current path generation and evolution. Time-to-failure characteristic values are then determined for the matching patterns based on the pre-computed time-to-failure characteristic values and electric attributes of geometric elements in each of the matching patterns. Based on the time-to-failure characteristic values, matching patterns most susceptible to time-dependent dielectric breakdown are identified and fixed.

Abstract: Various aspects of the disclosed technology relate to techniques of determining an across-chip distribution of temperature generated by on-chip devices. Effective thermal conductance and effective thermal capacity for each region of a plurality of regions of a layout design are first extracted. The effective thermal conductance for a region in a metal layer is determined based at least on density information of metal interconnect lines within the region and has components associated with directions of the metal interconnect lines. A thermal circuit is then constructed based on the effective thermal conductance, the effective thermal capacity and heat information of thermal nodes. The heat information of thermal nodes is determined based on an electrical simulation on the integrated circuit associated with the layout design. A thermal simulation is then performed on the thermal circuit to determine temperature information of the thermal nodes.

Abstract: Aspects of the disclosed technology relate to techniques of inserting stress-enhancing filler cells for leakage reduction. Stress analysis is first performed to identify devices with large leakage current in a layout design. An optimization zone in a row of cells that contains one or more of the devices with large leakage current is then determined. Stress-enhancing filler cells are inserted into the optimization zone to replace some or all of the one or more filler cells while placement of the cells in the optimization zone is adjusted based on a leakage reduction analysis.

Abstract: Various aspects of the disclosed technology relate to techniques of determining an across-chip distribution of temperature generated by on-chip devices. Effective thermal conductance and effective thermal capacity for each region of a plurality of regions of a layout design are first extracted. The effective thermal conductance for a region in a metal layer is determined based at least on density information of metal interconnect lines within the region and has components associated with directions of the metal interconnect lines. A thermal circuit is then constructed based on the effective thermal conductance, the effective thermal capacity and heat information of thermal nodes. The heat information of thermal nodes is determined based on an electrical simulation on the integrated circuit associated with the layout design. A thermal simulation is then performed on the thermal circuit to determine temperature information of the thermal nodes.

Abstract: Aspects of the invention relate to techniques for determining the electromigration features corresponding to layout design data. According to various examples of the invention, a circuit design is analyzed to determine voltages of nodes in an interconnect tree. From the voltages of the nodes, current density values and current directions for the segments of the interconnect tree are determined. Based on the current density values and the current directions, hydrostatic stress values for the nodes are computed under a steady-state condition and conservation of the conductive material within the interconnect tree. The electromigration susceptibility of the interconnect tree is then determined based on the computed hydrostatic stress values.

Abstract: Aspects of the invention relate to techniques for determining the electromigration features corresponding to layout design data. According to various examples of the invention, a circuit design is analyzed to determine voltages of nodes in an interconnect tree. From the voltages of the nodes, current density values and current directions for the segments of the interconnect tree are determined. Based on the current density values and the current directions, hydrostatic stress values for the nodes are computed under a steady-state condition and conservation of the conductive material within the interconnect tree. The electromigration susceptibility of the interconnect tree is then determined based on the computed hydrostatic stress values.

Abstract: A method for determining an effect of via/contact pattern density in via/contact etch rate of a wafer includes determining a neutral etchant species number flux intersecting each via/contact mouth as a function of local layout characteristics and determining variations in the neutral etchant species flux number as a function of the via/contact pattern density in a wafer scale. The comparison of these number fluxes provides the capability to discriminate an underetched or an overetched via/contact from normal vias/contacts satisfying an etch tolerance criterion. Chip designers can modify the layout design to minimize via/contact failures. Chip manufacturers can modify the etching process to minimize via/contact failures.

Abstract: An integrated circuit, or portion thereof, such as a CMOS device, includes an epitaxially grown dielectric on a silicon carbide base. The epitaxially grown dielectric forms a gate dielectric and the silicon carbide base serves as a channel region for the CMOS device. In various embodiments, the epitaxially grown dielectric may be a crystalline carbon or carbon-containing film.

Abstract: An integrated circuit, or portion thereof, such as a CMOS device, includes an epitaxially grown dielectric on a silicon carbide base. The epitaxially grown dielectric forms a gate dielectric and the silicon carbide base serves as a channel region for the CMOS device. In various embodiments, the epitaxially grown dielectric may be a crystalline carbon or carbon-containing film.

Abstract: A method of local reconstructing a grid containing a plurality of adjoining tetrahedrals wherein spheres cannot be constructed around each tetrahedral without including a vertex of another tetrahedral into a grid containing the tetrahedrals wherein spheres can be constructed around each tetrahedral without including a vertex of another tetrahedral. In the method, a face which adjoins two of the tetrahedrals is removed, thereby defining a hexahedron. If four vertices of the hexahedron are not on the same plane, an edge is constructed from a vertex of one tetrahedral to a vertex of another tetrahedral, such that three faces are defined inside the hexahedron, and such that the hexahedron is divided into three tetrahedrals, wherein spheres can be constructed around each tetrahedral without including a vertex of another tetrahedral. If four vertices of the hexahedron are on the same plane, a modified approach is used.

Abstract: An integrated circuit, or portion thereof, such as a CMOS device, includes an epitaxially grown dielectric on a silicon carbide base. The epitaxially grown dielectric forms a gate dielectric and the silicon carbide base serves as a channel region for the CMOS device. In various embodiments, the epitaxially grown dielectric may be a crystalline carbon or carbon-containing film.

Abstract: A method for planarizing a surface of an electrically conductive layer on a substrate, where the surface of the electrically conductive layer has relatively high features and relatively low features. A viscous material is applied to the surface of the electrically conductive layer, whereby at least the relatively low features are covered by the viscous material. The substrate is immersed in an electrically conductive solution. An electrical potential is applied between the electrically conductive layer and an electrode within the electrically conductive solution, whereby reaction kinetics favor erosion of the electrically conductive layer. The electrically conductive solution is agitated, thereby selectively uncovering the viscous material from at least features that are relatively high, and thereby preferentially planarizing at least the features that are relatively high.

Abstract: An integrated circuit, or portion thereof, such as a CMOS device, includes an epitaxially grown dielectric on a silicon carbide base. The epitaxially grown dielectric forms a gate dielectric and the silicon carbide base serves as a channel region for the CMOS device. In various embodiments, the epitaxially grown dielectric may be a crystalline carbon or carbon-containing film.

Abstract: A dual damascene-based interconnect structure which includes a liner of aluminum-0.5% copper alloy. The alloy can be implemented by depositing the alloy using a conventional PVD technique. To completely secure against copper atoms possibly penetrating through the aluminum-0.5% copper alloy, one or more Ta/TaN liners can be employed in addition to the aluminum-0.5% copper alloy liner. If Ta/taN is to be used, preferably the Ta/TaN is deposited before the aluminum-0.5% copper alloy is deposited.

Abstract: A method of forming a metal interconnect in an integrated circuit. A copper layer is formed over dielectric structures on the integrated circuit, where the dielectric structures have an upper level. The copper layer is planarized to be no higher than the upper level of the dielectric structures, without reducing the upper level of the dielectric structures. An electrically conductive capping layer is formed over all of the copper layer, without the capping layer forming over any of the dielectric structures.

Abstract: A method of forming a metal interconnect in an integrated circuit. A copper layer is formed over dielectric structures on the integrated circuit, where the dielectric structures have an upper level. The copper layer is planarized to be no higher than the upper level of the dielectric structures, without reducing the upper level of the dielectric structures. An electrically conductive capping layer is formed over all of the copper layer, without the capping layer forming over any of the dielectric structures.

Abstract: A process for etching oxide is disclosed wherein a reproducibly accurate and uniform amount of silicon oxide can be removed from a surface of an oxide previously formed over a semiconductor substrate by exposing the oxide to a nitrogen plasma in an etch chamber while applying an rf bias to a substrate support on which the substrate is supported in the etch chamber. The thickness of the oxide removed in a given period of time may be changed by changing the amount of rf bias applied to the substrate through the substrate support.

Abstract: The invention provides an algorithm for a methodology for interconnect design optimization by means of electromigration simulation. The algorithm provides for the capability to explore the effect of metal feature geometry, such as line width and height, a diffusion barrier (liner) material properties and thickness, via slop and corner rounding, and interconnect architecture (number of layers, feature density) on the probability of electromigration-induced and stressmigration-induced void nucleation. Implementation of all major driving forces for atom migration allows to predict a complete map of positions inside segments where void nucleation can be expected.