Abstract: A method includes forming a barrier layer on a substrate surface including at least one contact opening; forming an interconnect in the contact opening; and reducing the electrical conductivity of the barrier layer. A method including forming a barrier layer on a substrate surface including a dielectric layer and a contact opening, depositing a conductive material in the contact opening, removing the conductive material sufficient to expose the barrier layer on the substrate surface, and reducing the electrical conductivity of the barrier layer. An apparatus including a circuit substrate including at least one active layer including at least one contact point, a dielectric layer on the at least one active layer, a barrier layer on a surface of the dielectric layer, a portion of the barrier layer having been transformed from a first electrical conductivity to a second different and reduced electrical conductivity, and an interconnect coupled to the at least one contact point.

Abstract: A multiple stage method of electrolessly depositing a metal layer is presented. This method may have the two main stages of first forming a thin metal layer on a metal surface using an electroless plating solution containing activating agents that are highly reactive reducing agents, and second, forming a bulk metal layer over the thin metal layer by using an electroless plating solution containing mildly reactive reducing agents. Through this two stage method, the use of highly reactive reducing agents that may cause the formation of contaminant particles may be minimized. By minimizing the formation of contaminant particles in the electroless plating solution, the lifetime of the solution may be extended and the current leakage between metal interconnect lines may be reduced.

Abstract: Seed layer treatment to remove impurities in the seed layer that might lead to the formation of voids in interconnect circuit features. In one embodiment, the seed layer is heated in a reducing environment. In another embodiment, the seed layer is washed with a surfactant that is compatible with a surfactant used when forming the remainder of the circuit feature on the seed layer. Yet another embodiment combines both techniques.

Abstract: A method for sorting nanotubes and forming devices based upon selective nanotube types is provided. The disclosure provides methods of sorting semiconducting nanotubes useful in the formation of field effect transistors, diodes, and resistors. The disclosure also provides methods of sorting metallic nanotubes useful in the formation of interconnect devices.

Abstract: The present invention relates to a copper electroplating bath composition and method of using it for microelectronic device fabrication. In particular, the present invention relates to copper electroplating in the fabrication of interconnect structures in semiconductor devices. By use of the inventive copper electroplating bath composition, the incidence of voids in the interconnect structures is reduced.

Abstract: A method and apparatus for a semiconductor device having a semiconductor device having increased conductive material reliability is described. That method and apparatus comprises forming a conductive path on a substrate. The conductive path made of a first material. A second material is then deposited on the conductive path. Once the second material is deposited on the conductive path, the diffusion of the second material into the conductive path is facilitated. The second material has a predetermined solubility to substantially diffuse to grain boundaries within the first material.

Abstract: The invention provides bumps between a die and a substrate with a height greater than or equal to a height of a waveguide between the die and the substrate. The bumps may be formed on a die prior to that die being singulated from a wafer.

Abstract: The invention provides bumps between a die and a substrate with a height greater than or equal to a height of a waveguide between the die and the substrate. The bumps may be formed on a die prior to that die being singulated from a wafer.

Abstract: An embodiment of the invention provides a method for reducing within die thickness variations by modifying the concentration of components of a low-acid electroplating solution. For one embodiment, the leveler concentration is increased sufficiently to reduce within die thickness variations to a specified value. For one embodiment of the invention, the leveler and suppressor are increased to reduce within die thickness variations and substantially reduce a plurality of electroplating defects. In such an embodiment the combined concentration of leveler and suppressor is determined to maintain adequate gap fill.

Abstract: An embodiment of the invention provides a method for reducing electroplating defects by modifying the concentration of components of a high-acid electroplating solution. For one embodiment the suppressor concentration is increased sufficiently to substantially reduce a plurality of electroplating defects while maintaining adequate gap fill. In such an embodiment the concentration of a chloride in the high-acid electroplating solution is determined as low as possible to reduce defects while still sufficient catalyzing the suppressor to maintain adequate gap fill.

Abstract: A device includes an integrated circuit and a deposited tin in electrical contact with a portion of the integrated circuit. The deposited tin is formed by electrodeposition from a bath. The deposited tin includes a residue characteristic of the bath. The bath includes a bath-soluble tin compound, a strong acid, and a sulfopropylated anionic surfactant. In another aspect, a composition includes between approximately 20 and 40 grams per liter of one of stannous methane sulfonate, stannous sulfate, and a mixture thereof, between approximately 100 and 200 grams per liter of one of methanesulfonic acid, sulfuric acid, and a mixture thereof, and between approximately 1 and 2 grams per liter of one or more polyethyleneglycol alkyl-3-sulfopropyl diethers. In another aspect, a method includes electroplating tin with a current density of greater than approximately 30 mA/cm2 and a plating efficiency of greater than approximately 95%.

Abstract: Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.

Abstract: One or more semiconducting or conducting regions of a device such as a transistor may comprise molecular materials such as nanotubes or similar materials. Regions of a conductive alignment pattern used to align the nanotubes may be proximate to one or more ends of the nanotube. Additionally, a contact region may be proximate to each end of the nanotube to provide electrical contact to the nanotube. Nanotubes or the like may be in communication with device interconnection regions on a device substrate and may further be in communication with a package connection region on a package substrate.

Abstract: The present invention relates to a copper electroplating bath composition and method of using it for microelectronic device fabrication. In particular, the present invention relates to copper electroplating in the fabrication of interconnect structures in semiconductor devices. By use of the inventive copper electroplating bath composition, the incidence of voids in the interconnect structures is reduced.

Abstract: An apparatus for electroless spray deposition of a metal layer on a substrate, e.g., a Co shunt or barrier layer on a Cu layer on a semiconductor wafer, includes a processing chamber to hold the substrate, the processing chamber including at least one section movable between an open position to allow the substrate to be introduced into and removed from the processing chamber and a closed position to seal the processing chamber to allow for pressurization of the processing chamber. The processing chamber has an inlet to provide pressurizing gas, an exhaust line to exhaust pressurizing gas, a pressure regulator to regulate pressure there-within, and a sprayer to spray an electroless plating solution onto the substrate. A method for electroless spray deposition includes providing the in a processing chamber, sealing the processing chamber, pressurizing the processing chamber, regulating the pressure, and spraying an electroless plating solution onto the substrate.

Abstract: Embodiments of a method of bonding wafers together using a metal interlayer deposited on conductors of each wafer. Also disclosed is a wafer stack formed according to the method of wafer bonding using a metal interlayer.

Abstract: The present invention relates to a copper electroplating bath composition and method of using it for microelectronic device fabrication. In particular, the present invention relates to copper electroplating in the fabrication of interconnect structures in semiconductor devices. By use of the inventive copper electroplating bath composition, the incidence of voids in the interconnect structures is reduced.

Abstract: The inventor devised methods of forming interconnects that result in conductive structures with fewer voids and thus reduced electrical resistance. One embodiment of the method starts with an insulative layer having holes and trenches, fills the holes using a selective electroless deposition, and fills the trenches using a blanket deposition. Another embodiment of this method adds an anti-bonding material, such as a surfactant, to the metal before the electroless deposition, and removes at least some the surfactant after the deposition to form a gap between the deposited metal and interior sidewalls of the holes and trenches. The gap serves as a diffusion barrier. Another embodiments leaves the surfactant in place to serve as a diffusion barrier. These and other embodiments ultimately facilitate the speed, efficiency, or fabrication of integrated circuits.

Abstract: The present invention relates to a copper electroplating bath composition and method of using it for microelectronic device fabrication. In particular, the present invention relates to copper electroplating in the fabrication of interconnect structures in semiconductor devices. By use of the inventive copper electroplating bath composition, the incidence of voids in the interconnect structures is reduced.

Abstract: A method and apparatus for fabricating electrochemical copper interconnections between the component parts of an integrated circuit on a semiconductor device. A cathodic platter is provided that includes contact pins that contact the surface of a semiconductor wafer at predetermined locations during the electrochemical deposition process. The contact pins are arranged on the cathodic platter so that when placed on the surface of the semiconductor wafer the contact pins surround the perimetrical edges of each respective semiconductor device on the semiconductor wafer. Once the semiconductor wafer is properly positioned on the cathodic platter, a copper conductive layer can be electrochemically and uniformly deposited on the surface of the semiconductor device.