Abstract: A data processing device for variable length formats includes a control unit and a storage unit coupled to the control unit. Two data exchange buses are each coupled to a respective data input and to a respective data output of the storage unit. Two switches are coupled to the control unit and to respective data exchange buses. An arithmetic/logic unit is coupled to the control unit, to the switches and to the storage unit. A data shaft unit is coupled to the data exchange buses and to the control unit. A data masking unit is coupled to the data exchange buses, to the control unit and to the switches. This device enables the preparation for processing of multibyte data fields arbitrarily arranged with respect to the word boundaries in main storage. The data shift unit provides automatic alignment of the bytes of the operands relative to each other. The data masking unit masks irrelevant bytes of the first and last words of each operand.

Abstract: The method for diagnosing microprogrammed computers consists of locating malfunctioning computer circuits with the aid of basic control data from which individual basic control words are selected under the control of diagnostic control data, and activating those basic microorders contained in the selected basic control words which provide for execution of a predetermined diagnostic procedure. A device for effecting the above method comprises two groups of NAND gates, as well as two flip-flops. The first inputs of the NAND gates of each group are connected to respective outputs of a diagnostic control data storage and the second inputs are connected to the output of the flip-flop whose input is coupled to the output of a diagnostic unit. The outputs of the NAND gates of the first group are connected to the inputs of the control unit of a basic control data storage. The outputs of the NAND gates of the second group are connected via NOR gates to the activate inputs of respective decoders.

Abstract: The proposed information selection device includes an initial address register and a memory address forming unit. The forming unit is electrically connected to two coincidence circuits, a functional return address jump register and a control information decoder. The control information decoder is connected to a memory unit for storing control information. A constant register connected to the functional return address jump register. A control information register is connected to the control information decoder. The control information decoder is connected to each of the coincidence circuits. An analysis signal register is connected to an analysis signal forming decoder. A comparison code register and a comparison mask register are also included. To both coincidence circuits there is connected a comparison unit for comparing information, which is being analyzed, with a respective code.

Abstract: Disclosure is made of a method for dividing two numbers, whereby the numbers are converted to the binary code, and there is formed an address code of three digits of the dividend (the or remainder) by determining the position of the highest-order significant digit in the three high-order digits of the divisor. The address thus formed serves to produce three digits of the remainder, i.e. a digit corresponding to the highest-order significant digit of the divisor code and two adjacent higher-order digits. The three digits of the remainder are analyzed and, depending upon the result of the analysis, the code of either the single, or doubled, or trebled divisor is subtracted from the remainder code, whereby the next two quotient code digits are produced.Disclosure is further made of a device for effecting the proposed method for dividing two numbers, which comprises an arithmetic unit connected to dividend (or remainder) registers, buffer registers, divisor registers and quotient registers.