Patents by Inventor Valery S. Kaper
Valery S. Kaper has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230208364Abstract: Methods and apparatus for an amplifier including first and second transistors coupled in a stacked configuration with first and second current mirrors to provide respective bias signals to the amplifier transistors. A reference transistor is coupled to the first and second current mirrors for referencing the bias signals together.Type: ApplicationFiled: December 28, 2021Publication date: June 29, 2023Applicant: Raytheon CompanyInventors: John P. Bettencourt, Valery S. Kaper, Steven M. Lardizabal
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Patent number: 10447208Abstract: A circuit having (A) a transistor; (B) a bias circuit for providing setting a bias current for the transistor, the bias current having a current level in accordance with a reference current fed to the bias circuit; and (C) a bias current level controller, comprising: (i) a plurality of switches, each one of the switches comprises: a MOS FET and a GaN FET connected in a cascode configuration; and (ii) current source circuitry, comprising a plurality of current sources, each one of the current sources being connected between a voltage source and a corresponding one of the plurality of switches, the current source circuit combining currents produced by the current source in response a binary control signal fed to a gate of the MOS FET, the combined current providing the reference current fed to the bias circuit.Type: GrantFiled: December 15, 2017Date of Patent: October 15, 2019Assignee: Raytheon CompanyInventors: John P. Bettencourt, Valery S. Kaper, Steven M. Lardizabal
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Publication number: 20190190456Abstract: A circuit having (A) a transistor, (B) a bias circuit for providing setting a bias current for the transistor, the bias current having a current level in accordance with a reference current fed to the bias circuit; and (C) a bias current level controller, comprising: (i) a plurality of switches, each one of the switches comprises: a MOS FET and a GaN FET connected in a cascode configuration; and (ii) current source circuitry, comprising a plurality of current sources, each one of the current sources being connected between a voltage source and a corresponding one of the plurality of switches, the current source circuit combining currents produced by the current source in response a binary control signal fed to a gate of the MOS FET, the combined current providing the reference current fed to the bias circuit.Type: ApplicationFiled: December 15, 2017Publication date: June 20, 2019Applicant: Raytheon CompanyInventors: John P. Bettencourt, Valery S. Kaper, Steven M. Lardizabal
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Patent number: 9793859Abstract: An amplifier system having: an amplifier having a linear operating region where an output signal produced by the amplifier at the output terminal has a power level increasing proportionally with the increasing input signal power level up to a compression region of the amplifier where the output power is inhibited from increasing with increasing input signal power; and a DC current limiting circuit, coupled between a DC power supply and the amplifier, to: supply DC current from the DC power supply that is equal to quiescent current to the amplifier from the DC power supply when the amplifier operates in the linear region; enable the amplifier to draw increasing DC current from the DC power supply above the quiescent current with increasing input signal power until the output signal power reaches the desired compression point level which is lower than that of a stand-alone amplifier without the DC current limiting circuit; and, then limits the current drawn by the amplifier from the DC power supply.Type: GrantFiled: September 27, 2016Date of Patent: October 17, 2017Assignee: Raytheon CompanyInventors: Valery S. Kaper, John P. Bettencourt
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Patent number: 9584072Abstract: An amplifier having a pair of transistors arranged in a cascode amplifier arrangement serially connected to a first voltage source. A DC bias regulator is provided having: a DC bias circuit for producing a reference voltage at a control electrode of a first one of the pair of transistors: and a voltage combiner having a pair of inputs, a first of the pair of inputs being coupled to the reference voltage and a second one of the pair of inputs being coupled to the first voltage source. The DC bias regulator produces a DC bias voltage at a control electrode of a second one of the pair of transistors related to a combination of the reference voltage and the first voltage source.Type: GrantFiled: August 13, 2015Date of Patent: February 28, 2017Assignee: RAYTHEON COMPANYInventor: Valery S. Kaper
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Publication number: 20170047897Abstract: An amplifier having a pair of transistors arranged in a cascode amplifier arrangement serially connected to a first voltage source. A DC bias regulator is provided having: a DC bias circuit for producing a reference voltage at a control electrode of a first one of the pair of transistors: and a voltage combiner having a pair of inputs, a first of the pair of inputs being coupled to the reference voltage and a second one of the pair of inputs being coupled to the first voltage source. The DC bias regulator produces a DC bias voltage at a control electrode of a second one of the pair of transistors related to a combination of the reference voltage and the first voltage source.Type: ApplicationFiled: August 13, 2015Publication date: February 16, 2017Applicant: RAYTHEON COMPANYInventor: Valery S. Kaper
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Patent number: 9520836Abstract: A multi-stage amplifier having a first amplifier stage comprising: a pair of transistors arranged in a cascade amplifier arrangement; and an isolation circuit; and a second amplifier stage coupled to an output of the first amplifier stage; and bias regulator having a reference transistor. The cascode amplifier stage includes a pair of transistors arranged in a cascode amplifier arrangement. The bias regulator produces a reference current through the reference transistor and DC bias voltages for the control electrodes of each of the pair of transistors in the cascode amplifier arrangement and for the second stage's transistor as a function of the reference current through the reference transistor.Type: GrantFiled: August 13, 2015Date of Patent: December 13, 2016Assignee: Raytheon CompanyInventor: Valery S. Kaper
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Patent number: 9419580Abstract: A matching network requiring a predetermined shunt capacitance in a transformation of the impedance at the output to a transistor to a load. The matching network includes a vertically stacked shunt capacitor, for providing the entire predetermined capacitance, and a series DC blocking capacitor.Type: GrantFiled: October 31, 2014Date of Patent: August 16, 2016Assignee: Raytheon CompanyInventor: Valery S. Kaper
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Publication number: 20160126920Abstract: A matching network requiring a predetermined shunt capacitance in a transformation of the impedance at the output to a transistor to a load. The matching network includes a vertically stacked shunt capacitor, for providing the entire predetermined capacitance, and a series DC blocking capacitor.Type: ApplicationFiled: October 31, 2014Publication date: May 5, 2016Applicant: Raytheon CompanyInventor: Valery S. Kaper
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Patent number: 9270002Abstract: An interface for connecting a differential signal circuit having a differential signal output and a reference potential terminal to an input of a single ended signal circuit and a reference potential terminal. The interface includes a differential transmission line having a pair of electromagnetically coupled microwave transmission lines having first ends connected to the differential signal output and second ends, one of the second ends being connected to the single ended circuit input and the other one of the second ends being coupled to the reference potential terminals of the differential signal circuit and the single ended signal circuit.Type: GrantFiled: July 22, 2013Date of Patent: February 23, 2016Assignee: Raytheon CompanyInventors: Valery S. Kaper, Anthony Kopa
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Publication number: 20150022279Abstract: An interface for connecting a differential signal circuit having a differential signal output and a reference potential terminal to an input of a single ended signal circuit and a reference potential terminal. The interface includes a differential transmission line having a pair of electromagnetically coupled microwave transmission lines having first ends connected to the differential signal output and second ends, one of the second ends being connected to the single ended circuit input and the other one of the second ends being coupled to the reference potential terminals of the differential signal circuit and the single ended signal circuit.Type: ApplicationFiled: July 22, 2013Publication date: January 22, 2015Applicant: Raytheon CompanyInventors: Valery S. Kaper, Anthony Kopa
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Patent number: 8853745Abstract: A semiconductor structure, comprising: a substrate; a seed layer over an upper surface of the substrate; a semiconductor layer disposed over the seed layer; a transistor device in the semiconductor layer; wherein the substrate has an aperture therein, such aperture extending from a bottom surface of the substrate and terminating on a bottom surface of the seed layer; and an opto-electric structure disposed on the bottom surface of the seed layer.Type: GrantFiled: January 20, 2009Date of Patent: October 7, 2014Assignee: Raytheon CompanyInventors: Kamal Tabatabaie, Jeffrey R. LaRoche, Valery S. Kaper, John P. Bettencourt, Kelly P. Ip
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Patent number: 8154432Abstract: A system having: a digital pre-distortion circuit fed by a digital signal for distorting the digital signal; a digital to analog converter (DAC) core section coupled to an output of the calibration circuit for converting the distorted digital signal into a corresponding analog signal, the DAC core section performing the conversion in accordance with a control signal fed to the DAC core section; a power amplifier (PA) section coupled to an output of the DAC core section for amplifying power in the analog signal; and a calibration circuit coupled to the output of the power amplifier for producing, in response to the power in the power amplified analog signal, the control signal for the DAC core section.Type: GrantFiled: March 22, 2010Date of Patent: April 10, 2012Assignee: Raytheon CompanyInventors: Valery S. Kaper, John P. Bettencourt
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Publication number: 20110227770Abstract: A system having: a digital pre-distortion circuit fed by a digital signal for distorting the digital signal; a digital to analog converter (DAC) core section coupled to an output of the calibration circuit for converting the distorted digital signal into a corresponding analog signal, the DAC core section performing the conversion in accordance with a control signal fed to the DAC core section; a power amplifier (PA) section coupled to an output of the DAC core section for amplifying power in the analog signal; and a calibration circuit coupled to the output of the power amplifier for producing, in response to the power in the power amplified analog signal, the control signal for the DAC core section.Type: ApplicationFiled: March 22, 2010Publication date: September 22, 2011Applicant: Raytheon CompanyInventors: Valery S. Kaper, John P. Bettencourt
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Patent number: 7994550Abstract: A semiconductor structure comprising: a substrate; a seed layer supported by the substrate; an elemental semiconductor layer disposed over a first portion of the seed layer; and a compound semiconductor layer disposed on a second portion of the seed layer. The first portion of the seed layer is electrically insulated from the second portion of the seed layer. A first semiconductor device is formed in the elemental semiconductor layer. A second semiconductor device is formed in the compound semiconductor layer. The second semiconductor device includes: a first electrode in contact with a first region of the compound semiconductor layer; a second electrode in contact with a second region of the compound semiconductor layer; and a third electrode. The third electrode controls carriers passing in a third region of the compound semiconductor layer disposed between the first region and the second region. A fourth electrode is in electrical contact with the second portion of the seed layer.Type: GrantFiled: May 22, 2009Date of Patent: August 9, 2011Assignee: Raytheon CompanyInventors: Valery S. Kaper, John P. Bettencourt, Jeffrey R. LaRoche, Kamal Tabatabaie
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Publication number: 20100295104Abstract: A semiconductor structure comprising: a substrate; a seed layer supported by the substrate; an elemental semiconductor layer disposed over a first portion of the seed layer; and a compound semiconductor layer disposed on a second portion of the seed layer. The first portion of the seed layer is electrically insulated from the second portion of the seed layer. A first semiconductor device is formed in the elemental semiconductor layer. A second semiconductor device is formed in the compound semiconductor layer. The second semiconductor device includes: a first electrode in contact with a first region of the compound semiconductor layer; a second electrode in contact with a second region of the compound semiconductor layer; and a third electrode. The third electrode controls carriers passing in a third region of the compound semiconductor layer disposed between the first region and the second region. A fourth electrode is in electrical contact with the second portion of the seed layer.Type: ApplicationFiled: May 22, 2009Publication date: November 25, 2010Applicant: Raytheon CompanyInventors: Valery S. Kaper, John P. Bettencourt, Jeffrey R. LaRoche, Kamal Tabatabaie
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Patent number: 7834456Abstract: A semiconductor structure having a substrate, a seed layer over the substrate; a silicon layer disposed on the seed layer; a transistor device in the silicon layer; a III-V device disposed on the seed layer; and a plurality of electrical contacts, each one of the electrical contacts having a layer of TiN or TaN and a layer of copper or aluminum on the layer of TaN or TiN, one of the electrical contacts being electrically connected to the transistor and another one of the electrical contacts being electrically connected to the III-V device.Type: GrantFiled: January 20, 2009Date of Patent: November 16, 2010Assignee: Raytheon CompanyInventors: Kamal Tabatabaie, Michael S. Davis, Jeffrey R. LaRoche, Valery S. Kaper, John P. Bettencourt
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Publication number: 20100181601Abstract: A semiconductor structure, comprising: a substrate; a seed layer over an upper surface of the substrate; a semiconductor layer disposed over the seed layer; a transistor device in the semiconductor layer; wherein the substrate has an aperture therein, such aperture extending from a bottom surface of the substrate and terminating on a bottom surface of the seed layer; and an opto-electric structure disposed on the bottom surface of the seed layer.Type: ApplicationFiled: January 20, 2009Publication date: July 22, 2010Inventors: Kamal Tabatabaie, Jeffrey R. LaRoche, Valery S. Kaper, John P. Bettencourt, Kelly P. Ip
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Publication number: 20100181674Abstract: A semiconductor structure having a substrate, a seed layer over the substrate; a silicon layer disposed on the seed layer; a transistor device in the silicon layer; a III-V device disposed on the seed layer; and a plurality of electrical contacts, each one of the electrical contacts having a layer of TiN or TaN and a layer of copper or aluminum on the layer of TaN or TiN, one of the electrical contacts being electrically connected to the transistor and another one of the electrical contacts being electrically connected to the III-V device.Type: ApplicationFiled: January 20, 2009Publication date: July 22, 2010Inventors: Kamal Tabatabaie, Michael S. Davis, Jeffrey R. LaRoche, Valery S. Kaper, John P. Bettencourt
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Patent number: 7298217Abstract: A phase shifter is fed an input signal having a frequency f. A coupler is included fed by the input signal. The coupler has a pair of output terminals for providing a pair of signals having the frequency f and having a relative phase shift difference of m?/2 radians, where m is an integer. A switch is included having a pair of inputs, each one of the pair of inputs being coupled to a corresponding one of the pair of output terminals of the coupler. The switch has an output, one of the pair of inputs of the switch being coupled to the output of the switch selectively in accordance with a first control signal fed to the switch.Type: GrantFiled: December 1, 2005Date of Patent: November 20, 2007Assignee: Raytheon CompanyInventors: Michael G Adlerstein, Valery S. Kaper