Patents by Inventor Valery Teper
Valery Teper has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10374791Abstract: An electronic circuit with protection against eavesdropping by power analysis is provided. The electronic circuit includes: a storage element for storing a set of bits; a logic unit for processing the stored set of bits and providing a next state set of bits after two or more cycles, wherein in a first cycle, some of the stored set of bits are provided to the logic unit correctly and some are replaced by random values and in a last cycle, all of the stored set of bits are provided to the logic unit correctly; and a random bit generator that generates a random bit for each bit of the stored set of bits to determine which bits of the stored set of bits are to be provided correctly and which bits are to be replaced in each cycle.Type: GrantFiled: October 4, 2016Date of Patent: August 6, 2019Assignee: Winbond Electronics Corp.Inventors: Valery Teper, Nir Tasher
-
Patent number: 10019571Abstract: A system, comprising a logic circuit and delay circuitry, is described. The logic circuit is configured to perform a plurality of instances of a particular computation that is based on a plurality of inputs. The delay circuitry is configured to vary a power-consumption profile of the logic circuit over the plurality of instances, by applying, to the inputs, respective delays that vary over the instances, at least some of the delays varying independently from each other. Other embodiments are also described.Type: GrantFiled: March 13, 2016Date of Patent: July 10, 2018Assignee: WINBOND ELECTRONICS CORPORATIONInventors: Valery Teper, Uri Kaluzhny
-
Patent number: 9846187Abstract: An electronic circuit with protection against eavesdropping, including a first circuit element embedded in the electronic circuit, a second circuit element embedded in the electronic circuit, one or more connection lines between the first circuit element and the second circuit element, a first monitoring unit in the first circuit element for measuring capacitance of at least one of the connection lines between the first circuit element and the second circuit element, wherein the first monitoring unit is configured to identify changes in capacitance of the connection lines and to initiate actions to prevent eavesdropping in response to identifying changes.Type: GrantFiled: May 11, 2015Date of Patent: December 19, 2017Assignee: WINBOND ELECTRONICS CORPORATIONInventor: Valery Teper
-
Patent number: 9819657Abstract: An apparatus includes an interface and logic circuitry. The interface is configured to communicate over a communication link. The logic circuitry is configured to convert between a first stream of plaintext bits and a second stream of ciphered bits that are exchanged over the communication link, by applying a cascade of a stream ciphering operation and a mixing operation that cryptographically maps input bits to output bits.Type: GrantFiled: June 14, 2016Date of Patent: November 14, 2017Assignee: WINBOND ELECTRONICS CORPORATIONInventors: Nir Tasher, Moshe Alon, Valery Teper, Ziv Hershman, Uri Kaluzhny
-
Publication number: 20170262630Abstract: A system, comprising a logic circuit and delay circuitry, is described. The logic circuit is configured to perform a plurality of instances of a particular computation that is based on a plurality of inputs. The delay circuitry is configured to vary a power-consumption profile of the logic circuit over the plurality of instances, by applying, to the inputs, respective delays that vary over the instances, at least some of the delays varying independently from each other. Other embodiments are also described.Type: ApplicationFiled: March 13, 2016Publication date: September 14, 2017Inventors: Valery Teper, Uri Kaluzhny
-
Publication number: 20170214520Abstract: An electronic circuit with protection against eavesdropping by power analysis is provided. The electronic circuit includes: a storage element for storing a set of bits; a logic unit for processing the stored set of bits and providing a next state set of bits after two or more cycles, wherein in a first cycle, some of the stored set of bits are provided to the logic unit correctly and some are replaced by random values and in a last cycle, all of the stored set of bits are provided to the logic unit correctly; and a random bit generator that generates a random bit for each bit of the stored set of bits to determine which bits of the stored set of bits are to be provided correctly and which bits are to be replaced in each cycle.Type: ApplicationFiled: October 4, 2016Publication date: July 27, 2017Applicant: Winbond Electronics Corp.Inventors: Valery Teper, Nir Tasher
-
Patent number: 9703945Abstract: A computing device includes an input bridge, an output bridge, a processing core, and authentication logic. The input bridge is coupled to receive a sequence of data items for use by the device in execution of a program. The processing core is coupled to receive the data items from the input bridge and execute the program so as to cause the output bridge to output a signal in response to a given data item in the sequence, and the authentication logic is coupled to receive and authenticate the data items while the processing core executes the program, and to inhibit output of the signal by the output bridge until the given data item has been authenticated.Type: GrantFiled: August 13, 2013Date of Patent: July 11, 2017Assignee: WINBOND ELECTRONICS CORPORATIONInventors: Ziv Hershman, Valery Teper, Moshe Alon
-
Patent number: 9697310Abstract: There is provided a computerized mechanism for vulnerability evaluation in a layout having circuitry units as interceptors, comprising receiving a layout with interceptors incorporated therein at prearranged positions, virtually inducing faults in the layout by modeling a physical phenomenon that affects timings in the layout, detecting timing violations in the layout responsive to the induced faults based on discrepancies between the timings and provided specifications thereof determining vulnerability of the layout to faults according to detected faults, and wherein the method is performed on an at least one computerized apparatus configured to perform the method.Type: GrantFiled: November 2, 2015Date of Patent: July 4, 2017Assignee: WINBOND ELECTRONICS CORPORATIONInventor: Valery Teper
-
Publication number: 20170124238Abstract: There is provided a computerized mechanism for vulnerability evaluation in a layout having circuitry units as interceptors, comprising receiving a layout with interceptors incorporated therein at prearranged positions, virtually inducing faults in the layout by modeling a physical phenomenon that affects timings in the layout, detecting timing violations in the layout responsive to the induced faults based on discrepancies between the timings and provided specifications thereof determining vulnerability of the layout to faults according to detected faults, and wherein the method is performed on an at least one computerized apparatus configured to perform the method.Type: ApplicationFiled: November 2, 2015Publication date: May 4, 2017Inventor: Valery TEPER
-
Patent number: 9523722Abstract: A monolithic integrated circuit device may include a supply voltage glitch detector for detecting improper supply voltage conditions. Advantageously, the detection threshold of the supply voltage glitch detector is adaptively set based on the mode of operation of the device or a particular part of the device, which is internally known to the device based on certain inputs received by the device, such as commands, interrupts, control signals, and so forth.Type: GrantFiled: June 2, 2014Date of Patent: December 20, 2016Assignee: WINBOND ELECTRONICS CORPORATIONInventors: Nir Tasher, Valery Teper, Dennis Chin Cheng, Koying Huang
-
Publication number: 20160334449Abstract: An electronic circuit with protection against eavesdropping, including a first circuit element embedded in the electronic circuit, a second circuit element embedded in the electronic circuit, one or more connection lines between the first circuit element and the second circuit element, a first monitoring unit in the first circuit element for measuring capacitance of at least one of the connection lines between the first circuit element and the second circuit element, wherein the first monitoring unit is configured to identify changes in capacitance of the connection lines and to initiate actions to prevent eavesdropping in response to identifying changes.Type: ApplicationFiled: May 11, 2015Publication date: November 17, 2016Inventor: Valery TEPER
-
Patent number: 9471413Abstract: A method in a memory device that operates in a testing mode, includes receiving a vector to be written to the memory device. The vector is written to the memory device only if the vector belongs to a predefined set of test vectors. If the vector does not belong to the set of test vectors, the vector is converted to one of the test vectors, and the converted vector is written to the memory device.Type: GrantFiled: January 24, 2016Date of Patent: October 18, 2016Assignee: WINBOND ELECTRONICS CORPORATIONInventors: Nir Tasher, Uri Kaluzhny, Tsachi Weiser, Valery Teper
-
Publication number: 20160294792Abstract: An apparatus includes an interface and logic circuitry. The interface is configured to communicate over a communication link. The logic circuitry is configured to convert between a first stream of plaintext bits and a second stream of ciphered bits that are exchanged over the communication link, by applying a cascade of a stream ciphering operation and a mixing operation that cryptographically maps input bits to output bits.Type: ApplicationFiled: June 14, 2016Publication date: October 6, 2016Inventors: Nir Tasher, Moshe Alon, Valery Teper, Ziv Hershman, Uri Kaluzhny
-
Patent number: 9455962Abstract: An apparatus includes an interface and logic circuitry. The interface is configured to communicate over a communication link. The logic circuitry is configured to convert between a first stream of plaintext bits and a second stream of ciphered bits that are exchanged over the communication link, by applying a cascade of a stream ciphering operation and a mixing operation that cryptographically maps input bits to output bits.Type: GrantFiled: June 11, 2014Date of Patent: September 27, 2016Assignee: WINBOND ELECTRONICS CORPORATIONInventors: Nir Tasher, Moshe Alon, Valery Teper, Ziv Hershman, Uri Kaluzhny
-
Patent number: 9397663Abstract: An Integrated Circuit (IC) includes signal distribution circuitry and protection circuitry. The signal distribution circuitry is configured to distribute a high-fanout signal across the IC. The protection circuitry includes a plurality of logic stages and detection circuitry. The logic stages are configured to receive multiple instances of the signal that are sampled at multiple sampling points in the signal distribution circuitry. The logic stages are interconnected to drive one another in accordance with a given topology so as to propagate abnormalities indicative of faults occurring in the signal distribution circuitry. The detection circuitry is configured to detect a fault in the signal distribution circuitry in response to an abnormality propagating in the plurality of logic stages.Type: GrantFiled: June 28, 2015Date of Patent: July 19, 2016Assignee: WINBOND ELECTRONICS CORPORATIONInventors: Nir Tasher, Valery Teper, Leonid Azriel
-
Publication number: 20160139976Abstract: A method in a memory device that operates in a testing mode, includes receiving a vector to be written to the memory device. The vector is written to the memory device only if the vector belongs to a predefined set of test vectors. If the vector does not belong to the set of test vectors, the vector is converted to one of the test vectors, and the converted vector is written to the memory device.Type: ApplicationFiled: January 24, 2016Publication date: May 19, 2016Inventors: Nir Tasher, Uri Kaluzhny, Tsachi Weiser, Valery Teper
-
Patent number: 9343162Abstract: A non-volatile memory (NVM) device includes an NVM array, which is configured to store data, and control logic. The control logic is configured to receive data values for storage in the NVM array, and to write at least some of the received data values to the NVM array and simultaneously to write complements of the at least some of the received data values.Type: GrantFiled: August 25, 2014Date of Patent: May 17, 2016Assignee: WINBOND ELECTRONICS CORPORATIONInventors: Nir Tasher, Valery Teper, Dennis Chin Cheng, Boaz Tabachnik
-
Patent number: 9318221Abstract: A method in a memory device that operates in a testing mode, includes receiving a vector to be written to the memory device. The vector is written to the memory device only if the vector belongs to a predefined set of test vectors. If the vector does not belong to the set of test vectors, the vector is converted to one of the test vectors, and the converted vector is written to the memory device.Type: GrantFiled: April 3, 2014Date of Patent: April 19, 2016Assignee: Winbound Electronics CorporationInventors: Nir Tasher, Uri Kaluzhny, Tsachi Weiser, Valery Teper
-
Publication number: 20160028394Abstract: An Integrated Circuit (IC) includes signal distribution circuitry and protection circuitry. The signal distribution circuitry is configured to distribute a high-fanout signal across the IC. The protection circuitry includes a plurality of logic stages and detection circuitry. The logic stages are configured to receive multiple instances of the signal that are sampled at multiple sampling points in the signal distribution circuitry. The logic stages are interconnected to drive one another in accordance with a given topology so as to propagate abnormalities indicative of faults occurring in the signal distribution circuitry. The detection circuitry is configured to detect a fault in the signal distribution circuitry in response to an abnormality propagating in the plurality of logic stages.Type: ApplicationFiled: June 28, 2015Publication date: January 28, 2016Inventors: Nir Tasher, Valery Teper, Leonid Azriel
-
Patent number: 9223960Abstract: An apparatus for detecting tampering with a clock of a state-machine, comprising, a master state-machine having master states and driven by a master clock, the master states being switchable responsive to events, and an auxiliary state-machine having auxiliary states and driven by an auxiliary clock synchronous with the master clock, the auxiliary states being switchable responsive to a signal generated based at least on said events, consequently establishing a correspondence between the master states and the auxiliary states, thus ensuing that subsequent to tampering with the master clock the correspondence between the master states and the auxiliary states become discordant, thereby indicating that the master clock has been tampered with.Type: GrantFiled: July 31, 2014Date of Patent: December 29, 2015Assignee: WINBOND ELECTRONICS CORPORATIONInventors: Uri Kaluzhny, Tsachi Weiser, Valery Teper, Nir Tasher