Patents by Inventor Valluri R.M. Rao

Valluri R.M. Rao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6587605
    Abstract: A method and an apparatus providing an optical interconnection in an integrated circuit die. In one embodiment, an optical interconnection is used to optically interconnect a waveguide-based optical modulator through the insulating layer and back side of the semiconductor substrate of the integrated circuit die. In one embodiment, an insulating oxide layer is disposed between a semiconductor waveguide optical modulator and the back side of the semiconductor substrate. Optical conduits are disposed in the insulating oxide layer at the locations where light enters and exits the semiconductor waveguide optical modulator. In one embodiment, the optical conduits have indexes of refraction substantially equal to the indexes of refraction of the semiconductor substrate and the semiconductor waveguide optical modulator. Thus, attenuation of the light used to optically couple the semiconductor waveguide optical modulator through the back side of the semiconductor substrate is reduced.
    Type: Grant
    Filed: February 9, 2001
    Date of Patent: July 1, 2003
    Assignee: Intel Corporation
    Inventors: Mario J. Paniccia, Michael T. Morse, Valluri R. M. Rao
  • Patent number: 6393169
    Abstract: A method and an apparatus providing an optical interconnection in an integrated circuit die. In one embodiment, an optical interconnection is used to optically interconnect a waveguide-based optical modulator through the insulating layer and back side of the semiconductor substrate of the integrated circuit die. In one embodiment, an insulating oxide layer is disposed between a semiconductor waveguide optical modulator and the back side of the semiconductor substrate. Optical conduits are disposed in the insulating oxide layer at the locations where light enters and exits the semiconductor waveguide optical modulator. In one embodiment, the optical conduits have indexes of refraction substantially equal to the indexes of refraction of the semiconductor substrate and the semiconductor waveguide optical modulator. Thus, attenuation of the light used to optically couple the semiconductor waveguide optical modulator through the back side of the semiconductor substrate is reduced.
    Type: Grant
    Filed: January 6, 1999
    Date of Patent: May 21, 2002
    Assignee: Intel Corporation
    Inventors: Mario J. Paniccia, Michael T. Morse, Valluri R.M. Rao
  • Publication number: 20010031109
    Abstract: A method and an apparatus providing an optical interconnection in an integrated circuit die. In one embodiment, an optical interconnection is used to optically interconnect a waveguide-based optical modulator through the insulating layer and back side of the semiconductor substrate of the integrated circuit die. In one embodiment, an insulating oxide layer is disposed between a semiconductor waveguide optical modulator and the back side of the semiconductor substrate. Optical conduits are disposed in the insulating oxide layer at the locations where light enters and exits the semiconductor waveguide optical modulator. In one embodiment, the optical conduits have indexes of refraction substantially equal to the indexes of refraction of the semiconductor substrate and the semiconductor waveguide optical modulator. Thus, attenuation of the light used to optically couple the semiconductor waveguide optical modulator through the back side of the semiconductor substrate is reduced.
    Type: Application
    Filed: February 9, 2001
    Publication date: October 18, 2001
    Inventors: Mario J. Paniccia, Michael T. Morse, Valluri R.M. Rao
  • Patent number: 6150718
    Abstract: A method and an apparatus for performing circuit edits through the back side of a flip-chip packaged integrated circuit die. In one embodiment, a circuit edit is achieved by exposing first and second circuit edit connection targets through a semiconductor substrate of the integrated circuit die from the back side. Next, an insulating layer is deposited over the first and second circuit edit connection targets and the exposed semiconductor substrate. Next, the circuit edit connection targets are re-exposed through the insulating layer and a conductor is deposited over the re-exposed circuit edit connection targets and the deposited insulating layer from the back side of the integrated circuit to couple together the circuit edit connection targets.
    Type: Grant
    Filed: January 29, 1999
    Date of Patent: November 21, 2000
    Assignee: Intel Corporation
    Inventors: Richard H. Livengood, Valluri R. M. Rao, Jeffrey K. Greason
  • Patent number: 6125217
    Abstract: A method and an apparatus for providing an optical clock distribution network. In one embodiment, an optical source is configured to emit optical pulses at a desired clock frequency. The optical pulses are separated into a plurality of split optical pulses, each of which is received by a clock receiver node in a semiconductor die. In one embodiment, each clock receiver node locally generates a photocurrent in response to the split optical beams. Each of the photocurrents is locally converted into voltage and thus into local clock signals, which are used to clock the local area of the integrated circuit. In one embodiment, the semiconductor die includes an additional clock receiver node used to clock a clock generation circuit included in the semiconductor die. The clock generation circuit generates clock signals that are in phase with each other and the other clock signals generated throughout the semiconductor die.
    Type: Grant
    Filed: June 26, 1998
    Date of Patent: September 26, 2000
    Assignee: Intel Corporation
    Inventors: Mario J. Paniccia, Ian A. Young, Thomas P. Thomas, Valluri R. M. Rao
  • Patent number: 6075908
    Abstract: An optical modulator that modulates light through the semiconductor substrate through the back side of a flip chip packaged integrated circuit. The optical modulator of the present invention enables integrated circuit signals to be extracted through the back side of the semiconductor substrate. In one embodiment, an optical modulator is disposed within a flip chip packaged integrated circuit die. The optical modulator includes a deflector and a diffraction grating. An infrared light beam is directed through the back side of a silicon substrate of the integrated circuit die, deflected off the deflector through the diffraction grating and back out the back side of the integrated circuit die. The diffraction grating modulates the phase of a portion of the deflected light beam in response to an integrated circuit signal. A resulting diffraction interference occurs between the phase modulated portions and non-phase modulated portions of the deflected light beam.
    Type: Grant
    Filed: December 19, 1997
    Date of Patent: June 13, 2000
    Assignee: Intel Corporation
    Inventors: Mario J. Paniccia, Valluri R. M. Rao, Ian A. Young
  • Patent number: 6072179
    Abstract: A method and an apparatus for detecting an electric field in the active regions of an integrated circuit disposed in a semiconductor. In one embodiment, a laser beam is operated at a wavelength greater than approximately 0.9 .mu.m. The laser beam is focused onto a P-N junction, such as for example the drain of a MOS transistor, through the back side of the semiconductor substrate. As a result of free carrier absorption, the laser beam is partially absorbed near the P-N junction. When a signal is impressed on the P-N junction, the degree of free carrier absorption will be modulated in accordance with the modulation of the depletion region near the P-N junction. The laser beam passes through the P-N junction region, reflects off the oxide interface and metal behind the junction, and returns back through the P-N junction and back out of the silicon surface. Amplitude modulation in this reflected laser beam is detected with an optical detection system.
    Type: Grant
    Filed: August 7, 1998
    Date of Patent: June 6, 2000
    Assignee: Intel Corporation
    Inventors: Mario J. Paniccia, Valluri R. M. Rao, Wai Mun Yee
  • Patent number: 6049639
    Abstract: A method and an apparatus providing optical input/output in an integrated circuit. In one embodiment, optical modulators and demodulators, which are coupled to integrated circuit input/output nodes, are disposed on or within the back side semiconductor substrate of a flip chip packaged integrated circuit. Since a flip chip packaged integrated circuit die is utilized, full access to the optical modulators and demodulators is provided from the back side of the integrated circuit die for optical input/output. In one embodiment, a heat sink including a light source and an optical assembly is thermally and optically coupled to the back side of the integrated circuit die. A light beam is directed to the optical modulators and the deflected modulated light beam is routed and directed to the optical demodulators to realize optical input/output. In one embodiment, infrared light may be utilized such that the optical modulators and demodulators are disposed within a silicon semiconductor substrate.
    Type: Grant
    Filed: December 19, 1997
    Date of Patent: April 11, 2000
    Assignee: Intel Corporation
    Inventors: Mario J. Paniccia, Valluri R. M. Rao
  • Patent number: 5976980
    Abstract: A method and an apparatus providing a mechanical probe structure through the back side of an integrated circuit die. In one embodiment, semiconductor substrate is thinned from the back side of the integrated circuit die above a probe target. The probe target is then exposed and a thin insulating layer is formed over the exposed probe target and the nearby semiconductor substrate. The thin insulating layer provides electrical isolation between the exposed probe target and the bulk semiconductor substrate. The thin insulating layer also provides a base insulating platform for a probe pad that is subsequently deposited. After the insulating layer is formed over the exposed probe target and the nearby semiconductor substrate, the probe target is re-exposed through insulating layer such that a probe pad may be deposited over the probe target to provide electrical contact to the original probe target as well as provide a probe pad for mechanical probing purposes from the back side of the integrated circuit die.
    Type: Grant
    Filed: September 30, 1997
    Date of Patent: November 2, 1999
    Assignee: Intel Corporation
    Inventors: Richard H. Livengood, Paul Winer, Valluri R. M. Rao
  • Patent number: 5904486
    Abstract: A method and an apparatus for performing circuit edits through the back side of a flip-chip packaged integrated circuit die. In one embodiment, a circuit edit is achieved by exposing first and second circuit edit connection targets through a semiconductor substrate of the integrated circuit die from the back side. Next, an insulating layer is deposited over the first and second circuit edit connection targets and the exposed semiconductor substrate. Next, the circuit edit connection targets are re-exposed through the insulating layer and a conductor is deposited over the re-exposed circuit edit connection targets and the deposited insulating layer from the back side of the integrated circuit to couple together the circuit edit connection targets.
    Type: Grant
    Filed: September 30, 1997
    Date of Patent: May 18, 1999
    Assignee: Intel Corporation
    Inventors: Richard H. Livengood, Valluri R. M. Rao, Jeffrey K. Greason
  • Patent number: 4980019
    Abstract: An apparatus and a method to inhibit sputtering of undesirable material on to a dielectric layer of an integrated circuit being etched. After exposing the integrated circuit within its package, the leads of the integrated circuit are electrically coupled together by a metallic foil. The metallic foil is wrapped about the package to also provide thermal coupling, however, the integrated circuit is left exposed. Then, the integrated circuit is placed onto an etch-resilient plate disposed atop a cathode electrode. An opening in the plate allows direct placement of the integrated circuit onto the cathode. An etch-resilient cover is placed above the plate opening and the integrated circuit, but the cover has an opening to expose the integrated circuit. During etching, the cover inhibits sputtering from the leads, preform and bond wires.
    Type: Grant
    Filed: July 28, 1989
    Date of Patent: December 25, 1990
    Assignee: Intel Corporation
    Inventors: William Baerg, Valluri R. M. Rao
  • Patent number: 4961812
    Abstract: An apparatus and a method to inhibit sputtering of undesirable material onto a dielectric layer of an integrated circuit being etched. After exposing the integrated circuit within its package, the leads of the integrated circuit are electrically coupled together by a metallic foil. The metallic foil is wrapped about the package to also provide thermal coupling, however, the integrated circuit is left exposed. Then, the integrated circuit is placed onto an etch-resilient plate disposed atop a cathode electrode. An opening in the plate allows direct placement of the integrated circuit onto the cathode. An etch-resilient cover is placed above the plate opening and the integrated circuit, but the cover has an opening to expose the integrated circuit. During etching, the cover inhibits sputtering from the leads, preform and bond wires.
    Type: Grant
    Filed: September 13, 1988
    Date of Patent: October 9, 1990
    Assignee: Intel Corporation
    Inventors: William Baerg, Valluri R. M. Rao
  • Patent number: 4766372
    Abstract: An electron beam tester for fault detection and isolation in large and very large scale integrated circuits. An electron optical column focuses a primary beam of electrons on the surface of a circuit chip. An immersion extractor provides an electrical field to attract secondary electrons emitted from the irradiated surface. Secondary electrons are detected in an integral spectrometer. A wide bore final lens and integral high resolution double defection scan coils enable large area voltage contrast imaging as well as quantitative waveform measurement from internal nodes of the circuit chip.
    Type: Grant
    Filed: February 10, 1987
    Date of Patent: August 23, 1988
    Assignee: Intel Corporation
    Inventor: Valluri R. M. Rao