Patents by Inventor Vamshi Krishna Chillara
Vamshi Krishna Chillara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11536676Abstract: A multi-frequency signal may be used to induce voltage difference across a portion of a pipe. The voltage difference may be induced to take multi-frequency measurement of impedance characteristics of fluid inside the pipe. The multi-frequency measurement of the impedance characteristic of the fluid inside the pipe may be used to determine a characteristic of the fluid inside the pipe. This may be achieved by active integration of experimental data with high-resolution multi-frequency electrical impedance tomography (MFEIT) modeling.Type: GrantFiled: October 2, 2020Date of Patent: December 27, 2022Assignees: Triad National Security, LLC, Chevron U.S.A. Inc.Inventors: Vamshi Krishna Chillara, Maruti Kumar Mudunuru, Hari Selvi Viswanathan, Satish Karra, Bulbul Ahmmed, Jeffrey Foering App, Gary Michael Hoversten
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Publication number: 20220180028Abstract: A method for determining placement of MFEIT sensors in a horizontal well for detecting producing stages of the horizontal well. Embodiments involve computationally modeling the underlying physics of a well system and performing inversion to identify the MFEIT parameters (locations and conductivity) from electrical impedance measurements.Type: ApplicationFiled: December 9, 2020Publication date: June 9, 2022Inventors: Maruti Kumar Mudunuru, Vamshi Krishna Chillara, Bulbul Ahmmed, Satish Karra, Hari Selvi Viswanathan, Jeffrey Foering App, Gary Michael Hoversten, Christopher J. Champeaux, Jesus Barraza
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Publication number: 20220107283Abstract: A multi-frequency signal may be used to induce voltage difference across a portion of a pipe. The voltage difference may be induced to take multi-frequency measurement of impedance characteristics of fluid inside the pipe. The multi-frequency measurement of the impedance characteristic of the fluid inside the pipe may be used to determine a characteristic of the fluid inside the pipe. This may be achieved by active integration of experimental data with high-resolution multi-frequency electrical impedance tomography (MFEIT) modeling.Type: ApplicationFiled: October 2, 2020Publication date: April 7, 2022Inventors: Vamshi Krishna Chillara, Maruti Kumar Mudunuru, Hari Selvi Viswanathan, Satish Karra, Bulbul Ahmmed, Jeffrey Foering App, Gary Michael Hoversten
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Patent number: 11293279Abstract: Apparatus includes a plurality of geological subsurface electrical line sensors spaced apart from each other proximate a predetermined geological subsurface region of interest, with at least one of the electrical line sensors situated as a line source to produce a multi-frequency electrical impedance tomography source signal, and with at least one of the electrical line sensors situated as a line detector to receive the multi-frequency electrical impedance tomography response signal associated with the source signal that propagates through the predetermined geological subsurface region of interest, and a controller including a processor and a memory configured with instructions that, when executed by the processor, cause the processor to determine an electrical mapping over the predetermined geological subsurface region of interest based on the multi-frequency electrical impedance tomography source signal, response signal, and the spatial positions of the geological subsurface electrical line sensors.Type: GrantFiled: May 22, 2019Date of Patent: April 5, 2022Assignee: Triad National Security, LLCInventors: Satish Karra, Hari S. Viswanathan, Maruti Kumar Mudunuru, Vamshi Krishna Chillara, Dipen N. Sinha
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Patent number: 11264949Abstract: Apparatus and methods for rotary traveling wave oscillators (RTWOs) are disclosed. In certain embodiments, an RTWO system include an RTWO ring that carries a traveling wave, a plurality of selectable capacitors distributed around the RTWO ring and each operable in a selected state and an unselected state, and a decoder system that controls selection of the plurality of selectable capacitors based on a frequency tuning code. The frequency tuning code includes a fine tuning code and a coarse tuning code, and the decoder system is operable to maintain a constant number of capacitors that toggle state for each value of the fine tuning code.Type: GrantFiled: May 24, 2021Date of Patent: March 1, 2022Assignee: Analog Devices International Unlimited CompanyInventors: Vamshi Krishna Chillara, Declan D. Dalton, Colin G. Lyden, Hyman Shanan
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Publication number: 20210391828Abstract: Apparatus and methods for rotary traveling wave oscillators (RTWOs) are disclosed. In certain embodiments, an RTWO system include an RTWO ring that carries a traveling wave, a plurality of selectable capacitors distributed around the RTWO ring and each operable in a selected state and an unselected state, and a decoder system that controls selection of the plurality of selectable capacitors based on a frequency tuning code. The frequency tuning code includes a fine tuning code and a coarse tuning code, and the decoder system is operable to maintain a constant number of capacitors that toggle state for each value of the fine tuning code.Type: ApplicationFiled: May 24, 2021Publication date: December 16, 2021Inventors: Vamshi Krishna Chillara, Declan D. Dalton, Colin G. Lyden
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Patent number: 10931290Abstract: Aspects of this disclosure relate to reducing settling time of a ramp signal in a phase-locked loop. An offset signal can be applied to adjust an input signal provided to an integrator of a loop filter of the phase-locked loop to cause the settling time to be reduced. Disclosed methods of reducing settling time of a ramp signal can improve settling time of a ramp signal independent of the profile of the ramp signal.Type: GrantFiled: March 30, 2018Date of Patent: February 23, 2021Assignee: Analog Devices International Unlimited CompanyInventors: Vamshi Krishna Chillara, Declan M. Dalton, Pablo Cruz Dato
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Publication number: 20190305785Abstract: Aspects of this disclosure relate to reducing settling time of a ramp signal in a phase-locked loop. An offset signal can be applied to adjust an input signal provided to an integrator of a loop filter of the phase-locked loop to cause the settling time to be reduced. Disclosed methods of reducing settling time of a ramp signal can improve settling time of a ramp signal independent of the profile of the ramp signal.Type: ApplicationFiled: March 30, 2018Publication date: October 3, 2019Inventors: Vamshi Krishna Chillara, Declan M. Dalton, Pablo Cruz Dato
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Patent number: 10340926Abstract: Aspects of this disclosure relate to reducing settling time of a sawtooth ramp signal in a phase-locked loop. Information from a loop filter of the phase-locked loop can be stored and used within the loop filter so as to improve the settling time of the sawtooth ramp signal. In certain embodiments, the settling time of a periodic sawtooth ramp signal can be reduced to less than one microsecond. An output frequency at the end of the sawtooth chirp can be brought back to an initial value without significantly modifying phase error in disclosed embodiments.Type: GrantFiled: October 3, 2016Date of Patent: July 2, 2019Assignee: Analog Devices GlobalInventors: Vamshi Krishna Chillara, Declan M. Dalton, Pablo Cruz Dato
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Patent number: 10295580Abstract: A chip includes a phase-locked loop (PLL) and a test controller. The PLL includes an oscillator and a phase detector. In a normal mode, a first feedback loop includes a phase detector and an oscillator that generates an output based on a frequency input signal. In a test mode, the PLL is re-configured. The output of the loop filter can be decoupled from the input of the oscillator in the test mode and instead be coupled to the input of the phase detector. The oscillator can receive a test tuning signal provided by the test controller. In this test mode configuration, the PLL can measure the frequency of the oscillator.Type: GrantFiled: October 3, 2016Date of Patent: May 21, 2019Assignee: Analog Devices GlobalInventors: Vamshi Krishna Chillara, Pablo Cruz Dato, Declan M. Dalton
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Publication number: 20180097522Abstract: Aspects of this disclosure relate to reducing settling time of a sawtooth ramp signal in a phase-locked loop. Information from a loop filter of the phase-locked loop can be stored and used within the loop filter so as to improve the settling time of the sawtooth ramp signal. In certain embodiments, the settling time of a periodic sawtooth ramp signal can be reduced to less than one microsecond. An output frequency at the end of the sawtooth chirp can be brought back to an initial value without significantly modifying phase error in disclosed embodiments.Type: ApplicationFiled: October 3, 2016Publication date: April 5, 2018Inventors: Vamshi Krishna Chillara, Declan M. Dalton, Pablo Cruz Dato
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Publication number: 20180095119Abstract: A chip includes a phase-locked loop (PLL) and a test controller. The PLL includes an oscillator and a phase detector. In a normal mode, a first feedback loop includes a phase detector and an oscillator that generates an output based on a frequency input signal. In a test mode, the PLL is re-configured. The output of the loop filter can be decoupled from the input of the oscillator in the test mode and instead be coupled to the input of the phase detector. The oscillator can receive a test tuning signal provided by the test controller. In this test mode configuration, the PLL can measure the frequency of the oscillator.Type: ApplicationFiled: October 3, 2016Publication date: April 5, 2018Inventors: Vamshi Krishna Chillara, Pablo Cruz Dato, Declan M. Dalton
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Patent number: 9893734Abstract: Aspects of this disclosure relate to a digital phase-locked loop (DPLL) arranged to adjust output phase using a phase adjustment signal. In certain embodiments, the phase adjustment signal can be received in a signal path from an output of a time-to-digital converter of the DPLL to an input to the digitally controlled oscillator of the DPLL. Some embodiments relate to adjusting the output phase of the DPLL to reduce a relative phase difference between the output phase of the DPLL and an output phase of another DPLL.Type: GrantFiled: October 3, 2016Date of Patent: February 13, 2018Assignee: Analog Devices GlobalInventors: Vamshi Krishna Chillara, Declan M. Dalton
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Publication number: 20150137898Abstract: A buffering circuit for buffering an oscillator signal. The buffering circuit includes a plurality of PMOS and NMOS transistor pairs connected in parallel, each pair having connected gate terminals and connected drain terminals forming an inverter circuit, each pair arranged for receiving via a direct coupling an oscillator signal at its gate terminal, and each pair further being connected with an additional PMOS and NMOS transistor.Type: ApplicationFiled: November 13, 2014Publication date: May 21, 2015Applicant: Stichting IMEC NederlandInventors: Vamshi Krishna Chillara, Yao-Hong Liu, Robert Bogdan Staszewski