Abstract: A closed-loop IC design optimization process by automatically or manually creating design-specific cells with desired characteristics (e.g., performance, area, power, noise, etc.), which will be then implemented as a standard cell (also known hereafter as metacell), from a set of post-layout patterns. A post-layout pattern represents a part or whole of a standard cell and contains information regarding the pattern including, but not limited to, layout, timing, area, power and noise. As the metacells are created from post-layout patterns, the inaccuracies of prior dynamic library techniques are easily avoided. Such metacells, being design-specific, are optimized to satisfy the constraints imposed by the design context, thus bringing the powerful design-specific customization to standard cell-based design methodology.

Abstract: A closed-loop IC design optimization process by automatically or manually creating design-specific cells with desired characteristics (e.g., performance, area, power, noise, etc.), which will be then implemented as a standard cell (also known hereafter as metacell), from a set of post-layout patterns. A post-layout pattern represents a part or whole of a standard cell and contains information regarding the pattern including, but not limited to, layout, timing, area, power and noise. As the metacells are created from post-layout patterns, the inaccuracies of prior dynamic library techniques are easily avoided. Such metacells, being design-specific, are optimized to satisfy the constraints imposed by the design context, thus bringing the powerful design-specific customization to standard cell-based design methodology.

Abstract: A system and method for designing ICs, including the steps of: analyzing and optimizing a target IC design based on design-specific objectives; partitioning the optimized target IC design into pre-defined standard-cells from one or more libraries and creating design-specific cells specifically having unique functionality and characteristics not found amongst the standard-cells; identifying and determining a minimal subset of the standard-cells and design-specific cells, the interconnection of which represents the target IC design; generating the necessary views, including layout and characterizing of the design-specific cells included in a unique, minimal subset, wherein the IC design is subject to objectives and constraints of the target IC.

Abstract: The present invention pertains to an automated method for designing a integrated circuit (IC) design-specific cell, the method includes the steps of receiving a design specification for the design-specific cell, mapping a transistor-level representation of the design-specific cell, wherein the mapping is based on at least one, but perhaps plural design specifications, and evaluating the transistor-level representation of the design-specific cell for satisfaction of the design specification.

Abstract: An automated computer-implemented method, storage medium, and system for obtaining a pre-layout estimation of a characteristic of a standard cell including receiving a pre-layout netlist of a standard cell, applying at least one transformation to the pre-layout netlist to obtain an estimated representation, and characterizing the estimated representation to obtain a pre-layout estimation of the characteristic of the standard cell.

Abstract: A method and system for constructing, designing, and using a family of logic circuits based on methods of interconnecting transistors (or more generally, switches). The method includes the selective use of functionally redundant transistors to achieve target objectives, such as speed of operation, power dissipation, control over switching capacitances, noise characteristics and signal integrity. In accordance with the present invention, multiple topologies may be incorporated into the implementation of a single dynamic transistor topology. The logic circuit family provides flexibility by implementing different topologies for the various functionally redundant sub-networks of transistors. The method is applicable to any network of transistors whose characteristics depend, at least in part, on its implementation topology.

Abstract: The present invention relates to a method for minimizing the number of standard cells required to implement a digital circuit and for improving the characterization of new standard cells based on their context/environment. In addition, a systematic method that utilizes detailed characterization at the transistor-level on critical areas of the design for improved characterization and optimization of the entire design is presented.

Abstract: The present invention relates to a method for minimizing the number of standard cells required to implement a digital circuit and for improving the characterization of new standard cells based on their context/environment. In addition, a systematic method that utilizes detailed characterization at the transistor-level on critical areas of the design for improved characterization and optimization of the entire design is presented.

Abstract: A method and system for locating possible error or fault sites in a circuit or system. A set of nodes are chosen, using error models in some embodiments. By applying X values to the set of nodes in conjunction with three valued logic simulation output responses between the circuit and the specification are determined. Based on the comparison of the output responses between the circuit and the specification, an error probability can be assigned to the set of nodes. A ranked set of nodes is thereby produced with the highest ranked set of nodes being the most likely error or fault site. Furthermore, by determining the relationship of the inputs to the set of nodes to the outputs of the set of nodes in conjunction with test vectors and output responses determined in the specification, an error probability can also be assigned to the set of nodes. Use of symbolic logic variables can assist in determining the relationship of the inputs to the set of nodes to the outputs of the set of nodes.

Abstract: A method and system for constructing, designing, and using a family of logic circuits based on methods of interconnecting transistors (or more generally, switches). The method includes the selective use of functionally redundant transistors to achieve target objectives, such as speed of operation, power dissipation, control over switching capacitances, noise characteristics, signal integrity etc. In accordance with the present invention, multiple topologies may be incorporated into the implementation of a single dynamic transistor topology. The logic circuit family provides flexibility by implementing different topologies for the various functionally redundant sub-networks of transistors. The method is applicable to any network of transistors whose characteristics depend, at least in part, on its implementation topology.

Abstract: A system and method for verifying sequential circuits. A single pair of storage elements is selected from a single sequential circuit using the selected pairs of storage elements. A distinguishing sequence of test vectors is computed. Using the computed distinguishing sequence of test vectors, the other storage elements of the sequential circuits are distinguished. Based on the storage elements distinguished in the circuits, a correspondence between the storage elements of the circuits is determined and thus, equivalences between the circuits is found using combinational equivalence checking and the sequential circuit is verified. Alternatively, by using Boolean decision diagrams, the storage elements in the sequential circuit are distinguished and likewise distinguishing groups of storage elements are created.

Abstract: A system and method for designing ICs, including the steps of: analyzing and optimizing a target IC design based on design-specific objectives; partitioning the optimized target IC design into pre-defined standard-cells from one or more libraries and creating design-specific cells specifically having unique functionality and characteristics not found amongst the standard-cells; identifying and determining a minimal subset of the standard-cells and design-specific cells, the interconnection of which represents the target IC design; generating the necessary views, including layout and characterizing of the design-specific cells included in a unique, minimal subset, wherein the IC design is subject to objectives and constraints of the target IC.

Abstract: The present invention pertains to an automated method for designing a integrated circuit (IC) design-specific cell, the method includes the steps of receiving a design specification for the design-specific cell, mapping a transistor-level representation of the design-specific cell, wherein the mapping is based on at least one, but perhaps plural design specifications, and evaluating the transistor-level representation of the design-specific cell for satisfaction of the design specification.