Abstract: Disclosed is an elevator system in a building, the elevator system including a first elevator car for transporting a passenger between a plurality of building levels, the system including a controller that controls the elevator car, the controller: rendering a first determination that the passenger has requested elevator service from the first lobby, rendering a second determination to assign the elevator car to provide service to the passenger at a first lobby for the first level, effecting a first transmission to the elevator car to effect the second determination, rendering a third determination that the first lobby becomes unoccupied in a time period between effecting the first transmission and the elevator arriving at the first lobby for servicing the first passenger, rendering a fourth determination to release the elevator car from effecting the second determination, and effecting a second transmission to the elevator car to effect the fourth determination.

Abstract: Disclosed is an elevator system in a building, the elevator system including a first elevator car for transporting a passenger between a plurality of building levels, the system including a controller that controls the elevator car, the controller: rendering a first determination that the passenger has requested elevator service from the first lobby, rendering a second determination to assign the elevator car to provide service to the passenger at a first lobby for the first level, effecting a first transmission to the elevator car to effect the second determination, rendering a third determination that the first lobby becomes unoccupied in a time period between effecting the first transmission and the elevator arriving at the first lobby for servicing the first passenger, rendering a fourth determination to release the elevator car from effecting the second determination, and effecting a second transmission to the elevator car to effect the fourth determination.

Abstract: A read circuit includes a precharge circuit, coupled with at least a subset of bit lines and a sense circuit in a memory, and a transmission gate. The precharge circuit receives a first control signal and is operative during a first mode to set the bit lines to a first voltage level and to set an input to the sense circuit to a second voltage level. The transmission gate connects a given one of the bit lines with the sense circuit during a second mode as a function of a second control signal, such that when reading a first logic level from the selected memory cell, when the input of the sense circuit is connected with the given bit line, the given bit line is discharged to at least a third voltage, which is between the first and second voltage levels, thereby reducing a read access time in the memory.

Abstract: A read circuit includes a precharge circuit, coupled with at least a subset of bit lines and a sense circuit in a memory, and a transmission gate. The precharge circuit receives a first control signal and is operative during a first mode to set the bit lines to a first voltage level and to set an input to the sense circuit to a second voltage level. The transmission gate connects a given one of the bit lines with the sense circuit during a second mode as a function of a second control signal, such that when reading a first logic level from the selected memory cell, when the input of the sense circuit is connected with the given bit line, the given bit line is discharged to at least a third voltage, which is between the first and second voltage levels, thereby reducing a read access time in the memory.