Abstract: Illustrative embodiments manage deadlock in a data processing system during an IPL process that includes monitoring the usage of locks in the Hardware Object Model (HOM) of the data processing system. The process further includes detecting a deadlock condition in response to an indication of the IPL process in the data processing system entering a hung state when at least one lock is in use. The process also includes handling the deadlock condition by performing one or more of the following: recording error information for the deadlock condition, and terminating the IPL process.

Abstract: A method, system, and computer instructions for providing valid translation entries in the TCE table for all supported DMA addresses to prevent the occurrence of system errors due to prefetching. A page is reserved in system memory. This reserved page is made unavailable to the operating system and may not be utilized by any software in the system. The reserved page is also written with all bytes set to 0xFF. The system firmware then selects a region in system memory for the TCE table. The TCE table is initialized, with all entries within the TCE table initialized to be valid and contain the corresponding address of the reserved page.

Abstract: A method, system, and computer instructions for changing the lock-bits combination used to lock a resource upon receiving a system reset exception. The present invention forces the software to use different lock-bits combinations based on the number of occurrences of system reset exceptions. When a system reset exception is received, a system reset exception bit value in a special purpose register is updated based on the history of system reset exception occurrences. Based on the updated value in the system reset exception bit, the lock-bits combination for locking a resource is changed to allow the data processing system to reuse the resource with bad lock-bits. In this manner, the deadlocked resource is resolved, and a processor is not able to obtain an indefinitely held lock on system resources caused by system reset exceptions.

Abstract: A method for managing deadlock in a data processing system during an IPL process includes monitoring the usage of locks in the Hardware Object Model (HOM) of the data processing system. The process further includes detecting a deadlock condition in response to an indication of the IPL process in the data processing system entering a hung state when at least one lock is in use. The process further includes handling the deadlock condition by performing one or more of the following: recording error information for the deadlock condition, and terminating the IPL process.

Abstract: A method, computer program product, and a data processing system for maintaining operation of the data processing system in the event of a degraded system cooling condition is provided. A first temperature of a processor is identified as equaling or exceeding a processor throttling threshold. The operational frequency of the processor is reduced by a first frequency increment. The operational voltage of the processor is then reduced by a first voltage increment. Updated values of the processor temperature are periodically obtained and continued reductions in the frequency and operational voltage are made until the temperature indicates that the processor is operating in a stable throttle range. The frequency and operational voltage of the processor may be returned to normal levels when an updated temperature of the processor is less or equal to a throttle off threshold.

Abstract: A method, apparatus, and computer instructions for managing a set of processors. In response to a request to deallocate a processor assigned to a partition within the logical partitioned data processing system, the processor in the set of processors, is stopped. In response to stopping the processor, the processor is placed in an isolated state in which the processor is isolated from the partition. The processor is then placed in a pool of resources for later reassignment.

Abstract: A method, computer program product, and a data processing system for supporting memory addresses with holes is provided. A first physical address range allocated for system memory for an operating system run by a processor configured to support logical partitioning is virtualized to produce a first logical address range. A second physical address range allocated for system memory for the operating system is virtualized to produce a second logical address range. The first physical address range and the second physical address range are non-contiguous. Virtualization of the first and second physical address ranges is had such that the first logical address range and the second logical address range are contiguous. A memory mapped input/output physical address range that is intermediate the first physical address range and the second physical address range is virtualized to produce a third logical address range.

Abstract: A method, system, and computer instructions for providing valid translation entries in the TCE table for all supported DMA addresses to prevent the occurrence of system errors due to prefetching. The mechanism of the present invention reserves a page in system memory. This reserved page is made unavailable to the operating system and may not be utilized by any software in the system. The reserved page is also written with all bytes set to 0xFF. The system firmware then selects a region in system memory for the TCE table. The TCE table is initialized, with all entries within the TCE table initialized to be valid as well as contain the corresponding address of the reserved page. In this manner, all supported DMA page addresses will have valid TCE entries which translate the DMA addresses into the reserved page memory. Thus, prefetched DMA addresses will not encounter invalid DMA address translation, and crash the system.

Abstract: A method, system, and computer instructions for providing valid translation entries in the TCE table for all supported DMA addresses to prevent the occurrence of system errors due to prefetching. The mechanism of the present invention reserves a page in system memory. This reserved page is made unavailable to the operating system and may not be utilized by any software in the system. The reserved page is also written with all bytes set to 0xFF. The system firmware then selects a region in system memory for the TCE table. The TCE table is initialized, with all entries within the TCE table initialized to be valid as well as contain the corresponding address of the reserved page. In this manner, all supported DMA page addresses will have valid TCE entries which translate the DMA addresses into the reserved page memory. Thus, prefetched DMA addresses will not encounter invalid DMA address translation, and crash the system.

Abstract: A method, computer program product, and a data processing system for maintaining operation of the data processing system in the event of a degraded system cooling condition is provided. A first temperature of a processor is identified as equaling or exceeding a processor throttling threshold. The operational frequency of the processor is reduced by a first frequency increment. The operational voltage of the processor is then reduced by a first voltage increment. Updated values of the processor temperature are periodically obtained and continued reductions in the frequency and operational voltage are made until the temperature indicates that the processor is operating in a stable throttle range. The frequency and operational voltage of the processor may be returned to normal levels when an updated temperature of the processor is less or equal to a throttle off threshold.

Abstract: A method, apparatus, and computer instructions for changing an operating frequency for a system core logic used to interface to memory in the multi-processor data processing system. A determination is made as to whether the operating frequency should be changed from a default frequency to another frequency. Slave processors are placed in the multi-processor data processing system into a non-transactional mode, in response to determining the operating frequency should be changed from the default operating frequency to the another operating frequency. When the slave processors are in the non-transactional mode, the operating frequency is changed in the system core logic to other operating frequency by the master processor.

Abstract: A means for minimizing time for a system/device initial program load (IPL) in a system that will not support instruction prefetching when executing IPL code out of non-volatile memory. The IPL code is organized into a first portion and second portion. The first portion is executed from the non-volatile memory device to configure system memory; the first portion also provides initial control of cache inhibit and cache enable by way of software control. The cache-enabling code is strategically located at a memory page boundary such that the system hardware will disable instruction prefetching in an adjoining page lust past this cache enabling software code. After the first portion of IPL code configures system memory, the second portion is copied into memory through the L2 cache and executed from memory with cache enabled to allow speculative instruction prefetching.

Abstract: A method, apparatus, and computer instructions for recovering terminated partitions in a logical partitioned data processing system. A termination of a partition in a set of partitions associated with a host bridge in the logical partitioned data processing system is detected. The state of other partitions within the set of partitions is checked in response to detecting the termination. A recovery process is initiated if all partitions in the set of partitions have terminated. Input/output slots associated with the host bridge are reset to a normal state if the recovery process is successful. The set of partitions is rebooted after resetting the input/output slots associated with the host bridge without rebooting the logical partitioned data processing system.

Abstract: A logical partition (LPAR) computer system for managing partition configuration data is disclosed, which includes a nonvolatile memory, and a plurality of logical partitions, each running independently from the other logical partitions. The system also includes a console coupled to the computer system for accepting logical partition configuration data input by an operator. The configuration data entered by the operator specifies the processors, I/O, and memory allocated to each logical partition defined for the system. The system further includes a set of tables maintained in the nonvolatile memory for storing the logical partition configuration data, such that the logical partition configuration data is persistent across system power cycles.

Abstract: A interrupt is generated for all processors in a multiprocessor system when a critical datapath experiences an error. Serialization code in the interrupt handling routine for that interrupt suspends all processors except one and places the suspended processors in a waiting queue while the one processor handles the error. After the error has been handled, the remaining processors are allow to execute the interrupt handler, which simply exits detecting no error.

Abstract: A method, system, and product within a logically partitioned computer system including multiple, different partitions are disclosed for booting a partition using one of multiple, different firmware images. These multiple, different firmware images are stored in the computer system. One of the partitions is rebooted utilizing one of the firmware images without rebooting other ones of the partitions.

Abstract: A system for managing input/output drawers within a data processing system. A unique identifier is assigned to each of a plurality of drawers, and is used by the operating system to identify the drawers in the system regardless of how these drawers are interconnected. Another unique PCI-bridge identifier is assigned to each of a plurality of PCI Host bridges (PHBs) from all drawers, and is used by the operating system to perform input/output processes to devices associated with the plurality of PHBs such that the ODM object for each of the PHBs remains the same regardless of how the drawer is interconnected in the system. When a new drawer is added to the system, a new unique identifier is assigned to the new drawer ensuring that the unique identifiers previously assigned to the other drawers are not used to identify the new drawer.

Abstract: A method, apparatus, and computer instructions for managing memory blocks. In response to a request to deallocate a memory block from a partition, all processes are prevented from using the memory block. The memory block is isolated from the partition in response to preventing use of the memory block. The memory block is deallocated to form a free memory block.

Abstract: A method, system, and product are described for creating and managing affinity between memory and processors in logical partitions in a data processing system. The data processing system includes multiple processors. A memory affinity data structure is established. The memory affinity data structure identifies ones of the processors that have a close affinity with each one of multiple regions of the system memory. A memory affinity parameter is established and is utilized to determine whether memory affinity is required for each one of the logical partitions. In response to a determination that memory affinity is required for one of the logical partitions, the memory affinity data structure is utilized by a partition manager for the logical partition to allocate an optimal amount of memory that has a close affinity to ones of the processors that are assigned to the logical partition.

Abstract: In a computer system having a logical-partitioned server, each partition of the server is provided with its own separate lock and access corridor, in addition to a global lock. When the locking of a partition lock is followed by the locking of the global lock, the system is serialized. The partition locks are controlled by system firmware on behalf of an OS isolating each partition; however, the global lock is controlled by the system firmware to be unlocked independent of the lock/unlock status of the partition locks. In this manner, the ability or inability of an OS that issued a machine check interrupt to unlock its partition lock after the machine check analysis is complete is irrelevant; once the machine check analysis is complete, the system firmware unlocks the global lock, giving other partitions access to shared system resources to run their own machine checks.