Abstract: A dual alternator system includes a main alternator controlled by an electronic voltage regulator, a secondary alternator system having a secondary alternator controlled by a LIN controlled alternator voltage regulator and an electronic control unit (“ECU”) coupled to the LIN controller alternator voltage regulator by a LIN bus that that determines whether the secondary alternator should be off or operated to generate current. The ECU when it determines that the secondary alternator should be off sends a voltage setpoint signal to the LIN controlled alternator voltage regulator having a low value that is well below nominal system voltage. The ECU when it determines that the secondary alternator should be operated to provide current sends a voltage setpoint to the LIN controlled alternator voltage regulator having a high value that is well above a nominal system voltage and a MECL setpoint value.

Abstract: A dual alternator system includes a main alternator controlled by an electronic voltage regulator, a secondary alternator system having a secondary alternator controlled by a LIN controlled alternator voltage regulator and an electronic control unit (“ECU”) coupled to the LIN controller alternator voltage regulator by a LIN bus that that determines whether the secondary alternator should be off or operated to generate current. The ECU when it determines that the secondary alternator should be off sends a voltage setpoint signal to the LIN controlled alternator voltage regulator having a low value that is well below nominal system voltage. The ECU when it determines that the secondary alternator should be operated to provide current sends a voltage setpoint to the LIN controlled alternator voltage regulator having a high value that is well above a nominal system voltage and a MECL setpoint value.

Abstract: A method, computer program product, and a data processing system for maintaining operation of the data processing system in the event of a degraded system cooling condition is provided. A first temperature of a processor is identified as equaling or exceeding a processor throttling threshold. The operational frequency of the processor is reduced by a first frequency increment. The operational voltage of the processor is then reduced by a first voltage increment. Updated values of the processor temperature are periodically obtained and continued reductions in the frequency and operational voltage are made until the temperature indicates that the processor is operating in a stable throttle range. The frequency and operational voltage of the processor may be returned to normal levels when an updated temperature of the processor is less or equal to a throttle off threshold.

Abstract: A method, system, and computer instructions for changing the lock-bits combination used to lock a resource upon receiving a system reset exception. The present invention forces the software to use different lock-bits combinations based on the number of occurrences of system reset exceptions. When a system reset exception is received, a system reset exception bit value in a special purpose register is updated based on the history of system reset exception occurrences. Based on the updated value in the system reset exception bit, the lock-bits combination for locking a resource is changed to allow the data processing system to reuse the resource with bad lock-bits. In this manner, the deadlocked resource is resolved, and a processor is not able to obtain an indefinitely held lock on system resources caused by system reset exceptions.

Abstract: A method, computer program product, and a data processing system for maintaining operation of the data processing system in the event of a degraded system cooling condition is provided. A first temperature of a processor is identified as equaling or exceeding a processor throttling threshold. The operational frequency of the processor is reduced by a first frequency increment. The operational voltage of the processor is then reduced by a first voltage increment. Updated values of the processor temperature are periodically obtained and continued reductions in the frequency and operational voltage are made until the temperature indicates that the processor is operating in a stable throttle range. The frequency and operational voltage of the processor may be returned to normal levels when an updated temperature of the processor is less or equal to a throttle off threshold.

Abstract: A method, computer program product, and a data processing system for supporting memory addresses with holes is provided. A first physical address range allocated for system memory for an operating system run by a processor configured to support logical partitioning is virtualized to produce a first logical address range. A second physical address range allocated for system memory for the operating system is virtualized to produce a second logical address range. The first physical address range and the second physical address range are non-contiguous. Virtualization of the first and second physical address ranges is had such that the first logical address range and the second logical address range are contiguous. A memory mapped input/output physical address range that is intermediate the first physical address range and the second physical address range is virtualized to produce a third logical address range.

Abstract: A method, system, and computer instructions for providing valid translation entries in the TCE table for all supported DMA addresses to prevent the occurrence of system errors due to prefetching. The mechanism of the present invention reserves a page in system memory. This reserved page is made unavailable to the operating system and may not be utilized by any software in the system. The reserved page is also written with all bytes set to 0xFF. The system firmware then selects a region in system memory for the TCE table. The TCE table is initialized, with all entries within the TCE table initialized to be valid as well as contain the corresponding address of the reserved page. In this manner, all supported DMA page addresses will have valid TCE entries which translate the DMA addresses into the reserved page memory. Thus, prefetched DMA addresses will not encounter invalid DMA address translation, and crash the system.

Abstract: A method, apparatus, and computer instructions for changing an operating frequency for a system core logic used to interface to memory in the multi-processor data processing system. A determination is made as to whether the operating frequency should be changed from a default frequency to another frequency. Slave processors are placed in the multi-processor data processing system into a non-transactional mode, in response to determining the operating frequency should be changed from the default operating frequency to the another operating frequency. When the slave processors are in the non-transactional mode, the operating frequency is changed in the system core logic to other operating frequency by the master processor.

Abstract: A method, apparatus and program product for decreasing overall time for performing a system/device boot-up or initial program load (IPL). The system/device IPL code is organized into a plurality of portions, including a first portion and second portion. The first portion contains code to configure system memory, and is initially copied into the system's L2 cache. This first portion also provides initial control of cache inhibit and cache enable by way of software control. This first portion is executed from a non-volatile memory device to configure system memory and enable instruction caching by way of software control. The cache-enabling code is strategically located at a memory page boundary such that the system/device hardware will disable instruction prefetching in an adjoining page just past this cache enabling software code.