Abstract: A method of forming a multijunction solar cell including an upper subcell, a middle subcell, and a lower subcell, including providing first substrate for the epitaxial growth of semiconductor material; forming a first solar subcell on the substrate having a first band gap; forming a second solar subcell over the first solar subcell having a second band gap smaller than the first band gap; forming a grading interlayer over the second subcell, the grading interlayer having a third band gap greater than the second band gap; and forming a third solar subcell over the grading interlayer having a fourth band gap smaller than the second band gap such that the third subcell is lattice mis-matched with respect to the second subcell, wherein at least one of the bases of a solar subcell has an exponentially doped profile.

Abstract: A method of forming a multifunction solar cell including an upper subcell, a middle subcell, and a lower subcell, including providing first substrate for the epitaxial growth of semiconductor material; forming a first solar subcell on the substrate having a first band gap; forming a second solar subcell over the first solar subcell having a second band gap smaller than the first band gap; forming a grading interlayer over the second subcell, the grading interlayer having a third band gap greater than the second band gap; and forming a third solar subcell over the grading interlayer having a fourth band gap smaller than the second band gap such that the third subcell is lattice mismatched with respect to the second subcell, wherein at least one of the bases of a solar subcell has an exponentially doped profile.

Abstract: A method of forming a multijunction solar cell including an upper subcell, a middle subcell, and a lower subcell, including providing first substrate for the epitaxial growth of semiconductor material; forming a first solar subcell on the substrate having a first band gap; forming a second solar subcell over the first solar subcell having a second band gap smaller than the first band gap; forming a grading interlayer over the second subcell, the grading interlayer having a third band gap greater than the second band gap; and forming a third solar subcell over the grading interlayer having a fourth band gap smaller than the second band gap such that the third subcell is lattice mis-matched with respect to the second subcell, wherein at least one of the bases of a solar subcell has an exponentially doped profile.

Abstract: The disclosure relates to a process for performing processing steps at elevated temperatures on semiconductor devices while minimizing outdiffusion of arsenic therefrom wherein an arsenide containing semiconductor cover wafer is etched to form a flange on the periphery thereof, the cover wafer being placed over the active region of an arsenide containing wafer being processed to form a substantial seal therewith with the active region being spaced from the cover wafer. The wafers are then heated to elevated temperature with outdiffused arsenic being retained in the space between the wafers to raise the arsenic vapor pressure thereat and minimize arsenic outdiffusion thereby. As alternate embodiments, plural wafers being processed and cover wafers can alternately be stacked, one over the other. A further alternate embodiment comprises coating the surface of the cover wafer to avoid contamination of the production wafer with impurities which may exist in the cover wafer.