Patents by Inventor Vance H. Adams
Vance H. Adams has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9847389Abstract: An integrated circuit includes a device including an active region of the device, where the active region of the device includes a channel region having a transverse and a lateral direction. The device further includes an isolation region adjacent to the active region in a traverse direction from the active region, where the isolation region includes a first region located in a transverse direction to the channel region. The isolation region further includes a second region located in a lateral direction from the first region. The first region of the isolation region is under a stress of a first type and the second region of the isolative region is one of under a lesser stress of the first type or of under a stress of a second type being opposite of the first type.Type: GrantFiled: October 25, 2013Date of Patent: December 19, 2017Assignee: NXP USA, Inc.Inventors: Brian A. Winstead, Vance H. Adams, Paul A. Grudowski
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Publication number: 20140054704Abstract: An integrated circuit includes a device including an active region of the device, where the active region of the device includes a channel region having a transverse and a lateral direction. The device further includes an isolation region adjacent to the active region in a traverse direction from the active region, where the isolation region includes a first region located in a transverse direction to the channel region. The isolation region further includes a second region located in a lateral direction from the first region. The first region of the isolation region is under a stress of a first type and the second region of the isolative region is one of under a lesser stress of the first type or of under a stress of a second type being opposite of the first type.Type: ApplicationFiled: October 25, 2013Publication date: February 27, 2014Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Brian A. Winstead, Vance H. Adams, Paul A. Grudowski
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Patent number: 8569858Abstract: An integrated circuit includes a device including an active region of the device, where the active region of the device includes a channel region having a transverse and a lateral direction. The device further includes an isolation region adjacent to the active region in a traverse direction from the active region, where the isolation region includes a first region located in a transverse direction to the channel region. The isolation region further includes a second region located in a lateral direction from the first region. The first region of the isolation region is under a stress of a first type and the second region of the isolative region is one of under a lesser stress of the first type or of under a stress of a second type being opposite of the first type.Type: GrantFiled: December 20, 2006Date of Patent: October 29, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Brian A. Winstead, Vance H. Adams, Paul A. Grudowski
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Patent number: 7714318Abstract: An electronic device can include a transistor structure of a first conductivity type, a field isolation region, and a layer of a first stress type overlying the field isolation region. For example, the transistor structure may be a p-channel transistor structure and the first stress type may be tensile, or the transistor structure may be an n-channel transistor structure and the first stress type may be compressive. The transistor structure can include a channel region that lies within an active region. An edge of the active region includes the interface between the channel region and the field isolation region. From a top view, the layer can include an edge the lies near the edge of the active region. The positional relationship between the edges can affect carrier mobility within the channel region of the transistor structure.Type: GrantFiled: July 28, 2008Date of Patent: May 11, 2010Assignee: Freescale Semiconductor, IncInventors: Vance H. Adams, Paul A. Grudowski, Venkat R. Kolagunta, Brian A. Winstead
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Patent number: 7538002Abstract: A semiconductor fabrication process includes forming isolation structures on either side of a transistor region, forming a gate structure overlying the transistor region, removing source/drain regions to form source/drain recesses, removing portions of the isolation structures to form recessed isolation structures, and filling the source/drain recesses with a source/drain stressor such as an epitaxially formed semiconductor. A lower surface of the source/drain recess is preferably deeper than an upper surface of the recessed isolation structure by approximately 10 to 30 nm. Filling the source/drain recesses may precede or follow forming the recessed isolation structures. An ILD stressor is then deposited over the transistor region such that the ILD stressor is adjacent to sidewalls of the source/drain structure thereby coupling the ILD stressor to the source/drain stressor.Type: GrantFiled: February 24, 2006Date of Patent: May 26, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Da Zhang, Vance H. Adams, Bich-Yen Nguyen, Paul A. Grudowski
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Publication number: 20080296633Abstract: An electronic device can include a transistor structure of a first conductivity type, a field isolation region, and a layer of a first stress type overlying the field isolation region. For example, the transistor structure may be a p-channel transistor structure and the first stress type may be tensile, or the transistor structure may be an n-channel transistor structure and the first stress type may be compressive. The transistor structure can include a channel region that lies within an active region. An edge of the active region includes the interface between the channel region and the field isolation region. From a top view, the layer can include an edge the lies near the edge of the active region. The positional relationship between the edges can affect carrier mobility within the channel region of the transistor structure.Type: ApplicationFiled: July 28, 2008Publication date: December 4, 2008Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Vance H. Adams, Paul A. Grudowski, Venkat R. Kolagunta, Brian A. Winstead
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Patent number: 7420202Abstract: An electronic device can include a transistor structure of a first conductivity type, a field isolation region, and a layer of a first stress type overlying the field isolation region. For example, the transistor structure may be a p-channel transistor structure and the first stress type may be tensile, or the transistor structure may be an n-channel transistor structure and the first stress type may be compressive. The transistor structure can include a channel region that lies within an active region. An edge of the active region includes the interface between the channel region and the field isolation region. From a top view, the layer can include an edge the lies near the edge of the active region. The positional relationship between the edges can affect carrier mobility within the channel region of the transistor structure.Type: GrantFiled: November 8, 2005Date of Patent: September 2, 2008Assignee: Freescale Semiconductor, Inc.Inventors: Vance H. Adams, Paul A. Grudowski, Venkat R. Kolagunta, Brian A. Winstead
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Publication number: 20080150072Abstract: An integrated circuit includes a device including an active region of the device, where the active region of the device includes a channel region having a transverse and a lateral direction. The device further includes an isolation region adjacent to the active region in a traverse direction from the active region, where the isolation region includes a first region located in a transverse direction to the channel region. The isolation region further includes a second region located in a lateral direction from the first region. The first region of the isolation region is under a stress of a first type and the second region of the isolative region is one of under a lesser stress of the first type or of under a stress of a second type being opposite of the first type.Type: ApplicationFiled: December 20, 2006Publication date: June 26, 2008Inventors: Brian A. Winstead, Vance H. Adams, Paul A. Grudowski
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Patent number: 7271069Abstract: Mechanical stress control may be achieved using materials having selected elastic moduli. These materials may be selectively formed by implantation, may be provided as a plurality of buried layers interposed between the substrate and the active area, and may be formed by replacing selected portions of one or more buried layers. Any one or more of these methods may be used in combination. Mechanical stress control may be useful in the channel region of a semiconductor device to maximize its performance. In addition, these same techniques and structures may be used for other purposes besides mechanical stress control.Type: GrantFiled: April 21, 2005Date of Patent: September 18, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Marius K. Orlowski, Vance H. Adams
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Patent number: 7238580Abstract: A semiconductor fabrication process has recessed stress-inducing source/drain (SISD) structures that are formed using a multiple phase formation process. The SISD structures are semiconductor structures having a lattice constant that differs from a lattice constant of the semiconductor substrate in which the source/drain structures are recessed. The SISD structures preferably include semiconductor compound having a first element (e.g., silicon) and a second element (e.g., germanium or carbon). The SISD structure has a composition gradient wherein the percentage of the second element varies from the upper surface of the source/drain structure to a lower surface of the SISD structure. The SISD structure may include a first layer with a first composition of the semiconductor compound underlying a second layer with a second composition of the semiconductor compound. The second layer may include an impurity and have a higher percentage of the second element that the first layer.Type: GrantFiled: January 26, 2005Date of Patent: July 3, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Marius K. Orlowski, Vance H. Adams, Chun-Li Liu, Matthew W. Stoker
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Patent number: 7205202Abstract: Mechanical stress control may be achieved using materials having selected elastic moduli. These materials may be selectively formed by implantation, may be provided as a plurality of buried layers interposed between the substrate and the active area, and may be formed by replacing selected portions of one or more buried layers. Any one or more of these methods may be used in combination. Mechanical stress control may be useful in the channel region of a semiconductor device to maximize its performance. In addition, these same techniques and structures may be used for other purposes besides mechanical stress control.Type: GrantFiled: April 21, 2005Date of Patent: April 17, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Marius K. Orlowski, Vance H. Adams
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Patent number: 7166897Abstract: A method and apparatus is presented that provides performance enhancement in a semiconductor device. In one embodiment, a first current region (64, 76, 23), a channel region and a second current region (75, 33, 66) are adjacent each other. The second current region (75, 33, 66) has a content of a first element of an alloy greater than a content of the first element in the first current region (64, 76, 23), wherein the second current region (75, 33, 66) has a content of the first element greater than a content of the first element in the channel region, the alloy further comprises a second element, the first element has a first valence number, and the second element has a second valence number. Furthermore, the sum of the first valence number and the second valence number is eight.Type: GrantFiled: August 24, 2004Date of Patent: January 23, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Marius K. Orlowski, Vance H. Adams, Chun-Li Liu, Brian A. Winstead
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Patent number: 7161199Abstract: A transistor comprises a source and drain positioned within an active region. A gate overlies a channel area of the active region, wherein the channel region separates the source and drain. The transistor further comprises at least one stress modifier and capacitive reduction feature extending from the source to the drain and underlying the gate for reducing capacitance associated with the gate, source and drain. The at least one stress modifier and capacitive reduction feature comprises dielectric and includes a shape defined at least partially by the active region.Type: GrantFiled: August 24, 2004Date of Patent: January 9, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Jian Chen, Michael A. Mendicino, Vance H. Adams, Choh-Fei Yeap, Venkat R. Kolagunta
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Patent number: 7064396Abstract: An integrated circuit with both P-channel transistors (823) and N-channel transistors (821) with different spacer insulating region widths. In one example, the outer sidewall spacer (321) of the N-channel transistors is removed while the P-channel regions (115) are masked such that the spacer insulating region widths of the N-channel transistors is less than the spacer insulating region widths of the P-channel transistors. Also, the drain/source silicide regions (805) of the N-channel transistors are located closer to the gates (117) of those transistors than the P-channel source/drain suicide regions (809) are located to the gates (119) of those transistors.Type: GrantFiled: March 1, 2004Date of Patent: June 20, 2006Assignee: Freescale Semiconductor, Inc.Inventors: Jian Chen, Vance H. Adams, Choh-Fei Yeap
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Patent number: 7041576Abstract: An integrated circuit with a first plurality of transistors formed on a first wafer and second plurality of transistors formed on a second wafer. At least a substantial majority of the transistor of the first transistor are of a first conductivity type and at least a substantial majority of the transistors of the second plurality are of a second conductivity type. After wafers are bonded together, a portion of the second wafer is removed wherein the strain of the channels of the second plurality of transistors is more compressive than the strain of the channels of the first plurality of transistors.Type: GrantFiled: May 28, 2004Date of Patent: May 9, 2006Assignee: Freescale Semiconductor, Inc.Inventors: Scott K. Pozder, Salih M. Celik, Byoung W. Min, Vance H. Adams