Abstract: A zero intermediate frequency (ZIF) radio frequency (RF) digital mixer (200) includes a low noise amplifier (LNA) (203), a first RF mixer stage (205) for mixing an RF signal from the at least one LNA with a first local oscillator signal operating a first predetermined frequency. A second RF mixer stage (207) is then utilized for mixing in-phase (I) and quadrature (Q) digital signals from the first RF mixer stage (205) with a plurality of second local oscillator signals (LO) operating at a second predetermined frequency. The invention significantly improves current drain by eliminating the need for a linear transconductance stage while still maintaining high degrees of isolation and linearity.

Abstract: A zero intermediate frequency (ZIF) radio frequency (RF) digital mixer (200) includes a low noise amplifier (LNA) (203), a first RF mixer stage (205) for mixing an RF signal from the at least one LNA with a first local oscillator signal operating a first predetermined frequency. A second RF mixer stage (207) is then utilized for mixing in-phase (I) and quadrature (Q) digital signals from the first RF mixer stage (205) with a plurality of second local oscillator signals (LO) operating at a second predetermined frequency. The invention significantly improves current drain by eliminating the need for a linear transconductance stage while still maintaining high degrees of isolation and linearity.

Abstract: A mixer circuit (230) comprises a double balanced mixer (370) including a first pair of transistors (Q3, Q4) and a second pair of transistors (Q5, Q6) and a differential amplifier (330) including a pair of transistors (Q1, Q2) coupled to a first reference voltage (302). A coupling element (C3) is inserted between a common emitter node (391) of the first pair of transistors (Q3, Q4) of the double balanced mixer (370) and the output node of one of the pair of transistors (Q1) of the RF input stage (330), and a coupling element (C4) is inserted between a common emitter node (392) of the second pair of transistors (Q5, Q6) of the double balanced mixer (370) and the output node of the other pair of transistors (Q2) of the differential amplifier (330).

Abstract: A zero-intermediate frequency receiver circuit (11) for receiving a radio frequency signal detected by an antenna (14). The receiver circuit (10) comprises a second local oscillator circuit (25) and an oscillator circuit (60) of a phase locked loop demodulator (36) which are identical and track each other so as to provide a more accurate reference for processing a demodulated signal. A current reference (39) providing a current reference signal utilized by the second local oscillator circuit (25) and the oscillator circuit (60) of the phase locked loop demodulator (36).

Abstract: A phase locked loop (PLL) circuit for use as a demodulator and other applications. The PLL circuit (200) comprises a phase detector (210), a transconductance amplifier (212) and a current controlled oscillator (ICO) (214). The phase detector has two signal inputs and two outputs, and detects a phase difference between signals at its inputs. A capacitor C1 is connected to the output of phase detector (210) and develops an output voltage signal vo(t). A transconductance amplifier (212) is coupled to the capacitor C1 and converts the output voltage signal vo(t) to an output current signal. The ICO (214) is coupled to the transconductance amplifier (212) and the second output of the phase detector (210) and generates an output signal having a frequency which is proportional to an input current signal. The output signal of the ICO (214) is coupled to the second signal input of the phase detector (212).

Abstract: A selective call receiver (100) includes a radio frequency amplifier (202) having an output power level that is controllable. A radio frequency level sensor (500) generates a sensor output signal in response to an input signal level received at the radio frequency amplifier (202). The sensor output signal is conditioned by a filter (401, 402) to generate a control signal representing an effective value of the input signal level received at the radio frequency amplifier (202). The control signal is then coupled to an amplifier output power level adjustment circuit (403) that operates to adjust a power gain of the radio frequency amplifier (202) in an unconditionally stable feed-forward manner such that the output power level remains substantially constant when the input signal level sensed by the radio frequency level sensor (500) substantially reaches or exceeds a predetermined signal overload level.