Abstract: A method and apparatus for analyzing a semiconductor device having a diode formed therein. In its broadest sense, the invention involves irradiating the semiconductor device with electromagnetic radiation while monitoring the leakage current output from the diode contained in the semiconductor device. If the semiconductor device is present and properly soldered to the printed circuit board, an increase in the leakage current will be observed during the irradiation process. The increase in leakage current is also representative of the presence of intact bond wires at both the pin under test and the ground pin. The invention in a preferred form is shown to include a voltage source, electrically connected to the diode, for biasing the diode in a reverse direction, a current monitor, connected to monitor the leakage current from the diode and an electromagnetic radiation generator, positioned to provide electromagnetic radiation incident on the semiconductor device.

Abstract: Disclosed is a system for determining whether semiconductor components are present and properly connected to a printed circuit board. The semi-conductor material between two pins of an integrated circuit forms a lateral NPN transistor, having its base connected directly to the substrate connection pin of the component. A constant voltage source is applied to the lateral transistor collector pin of the component being tested, and allowed to stabilize. A current or voltage source is then connected to the emitter pin of the lateral transistor, typically an adjacent pin, and a current or voltage pulse is applied to this pin. The current on the collector pin is then monitored and if a corresponding current pulse is detected, the emitter and collector pins, as well as the substrate connection pin of the component, are properly connected to the printed circuit board.

Abstract: An improved digital testing device is presented which includes the capability to detect and avoid a pair of common sources of measurement error. One source of error occurs when measurements are made within a Setup time before a transition in the signal under test or during a Hold time after such a transition. This device includes the ability to detect when this occurs and to insert a relative delay between the measurements and transitions to eliminate such errors. The device also detects the existence of a 3-state condition of a point of the circuit under test during the period of a measurement and provides an output indication when such occurs.

Abstract: A method and apparatus are disclosed for reducing the likelihood of damage to digital logic devices under test or located in close electrical proximity to the device under test while attempting to locate faults in circuit assemblies using digital incircuit test techniques.