Abstract: A glitch detector includes a metastability detector circuit, a reference storage circuit, and a pattern comparison circuit. The metastability detector circuit is configured to generate state signals at each cycle of the clock signal. The reference storage circuit is configured to store a logic state of each state signal based on a delayed version of the clock signal, and generate reference signals. A logic state of each reference signal is equal to a logic state of a corresponding state signal generated during a previous cycle of the clock signal. The pattern comparison circuit is configured to receive the state signals generated during a current cycle of the clock signal, the reference signals, and first and second values, and generate clock and voltage glitch signals based on first and second patterns that are associated with the state signals generated during the current cycle and the reference signals, respectively.

Abstract: A glitch detector includes a metastability detector circuit, a reference storage circuit, and a pattern comparison circuit. The metastability detector circuit is configured to generate state signals at each cycle of the clock signal. The reference storage circuit is configured to store a logic state of each state signal based on a delayed version of the clock signal, and generate reference signals. A logic state of each reference signal is equal to a logic state of a corresponding state signal generated during a previous cycle of the clock signal. The pattern comparison circuit is configured to receive the state signals generated during a current cycle of the clock signal, the reference signals, and first and second values, and generate clock and voltage glitch signals based on first and second patterns that are associated with the state signals generated during the current cycle and the reference signals, respectively.

Abstract: A glitch detector includes a metastability detector circuit, a reference storage circuit, and a pattern comparison circuit. The metastability detector circuit is configured to generate state signals at each cycle of the clock signal. The reference storage circuit is configured to store a logic state of each state signal based on a delayed version of the clock signal, and generate reference signals. A logic state of each reference signal is equal to a logic state of a corresponding state signal generated during a previous cycle of the clock signal. The pattern comparison circuit is configured to receive the state signals generated during a current cycle of the clock signal, the reference signals, and first and second values, and generate clock and voltage glitch signals based on first and second patterns that are associated with the state signals generated during the current cycle and the reference signals, respectively.

Abstract: A glitch detector includes a metastability detector circuit, a reference storage circuit, and a pattern comparison circuit. The metastability detector circuit is configured to generate state signals at each cycle of the clock signal. The reference storage circuit is configured to store a logic state of each state signal based on a delayed version of the clock signal, and generate reference signals. A logic state of each reference signal is equal to a logic state of a corresponding state signal generated during a previous cycle of the clock signal. The pattern comparison circuit is configured to receive the state signals generated during a current cycle of the clock signal, the reference signals, and first and second values, and generate clock and voltage glitch signals based on first and second patterns that are associated with the state signals generated during the current cycle and the reference signals, respectively.

Abstract: A fixed-width pulse generator includes a metastability detector circuit, a delay signal generator, and a combinational logic circuit. The metastability detector circuit is configured to receive a trigger signal and generate state detection signals. The delay signal generator is configured to receive the state detection signals and the trigger signal, and delay the trigger signal by two different delay values to generate two different delayed signals. One of the delay values is based on the state detection signals. The combinational logic circuit is configured to receive the two delayed signals and an error signal, and generate a fixed-width pulse that remains constant over process, voltage, and temperature variations.

Abstract: An integrated circuit (IC) having a clock switch that switches the system clock between an internal clock and an external clock based on whether or not the IC has finished downloading device configuration at boot and on whether or not the internal clock is functional. Further restrictions on the use of the external clock are imposed by the clock switch based on a life-cycle state of the IC. The use of the clock switch makes it significantly more difficult for the clock to be tampered with, thereby protecting the security settings of the IC and/or preventing unauthorized access to secure data stored on the IC using an external-clock-based security attack.

Abstract: An integrated circuit (IC) having a clock switch that switches the system clock between an internal clock and an external clock based on whether or not the IC has finished downloading device configuration at boot and on whether or not the internal clock is functional. Further restrictions on the use of the external clock are imposed by the clock switch based on a life-cycle state of the IC. The use of the clock switch makes it significantly more difficult for the clock to be tampered with, thereby protecting the security settings of the IC and/or preventing unauthorized access to secure data stored on the IC using an external-clock-based security attack.

Abstract: An integrated circuit (IC) is connected to an automated test equipment (ATE) with pogo pins. The IC includes an analog-to-digital converter (ADC), a voltage controlled oscillator (VCO), and a compensation circuit. The ATE provides reference voltage signals to the ADC by way of the pogo pins. A potential drop across a pogo pin introduces an error in a reference voltage signal that is reflected in a digital signal generated by the ADC. The VCO generates reference frequency signals corresponding to the reference voltage signals. The compensation circuit receives the reference frequency signals and the digital signal and generates a compensation factor signal. The compensation circuit multiplies the compensation factor signal and the digital signal to generate a compensated digital signal to compensate for the error introduced by the potential drop across the pogo pins.

Abstract: An integrated circuit (IC) is connected to an automated test equipment (ATE) with pogo pins. The IC includes an analog-to-digital converter (ADC), a voltage controlled oscillator (VCO), and a compensation circuit. The ATE provides reference voltage signals to the ADC by way of the pogo pins. A potential drop across a pogo pin introduces an error in a reference voltage signal that is reflected in a digital signal generated by the ADC. The VCO generates reference frequency signals corresponding to the reference voltage signals. The compensation circuit receives the reference frequency signals and the digital signal and generates a compensation factor signal. The compensation circuit multiplies the compensation factor signal and the digital signal to generate a compensated digital signal to compensate for the error introduced by the potential drop across the pogo pins.