Abstract: The invention is notably directed to a method of processing data in-memory. The method applies electrical signals to at least two input lines, which correspond to at least two rows. These two rows include at least one of the K rows and at least one of the L rows. This causes to obtain output signals in output of the M output lines, wherein the output signals depend on target values and operand values, in accordance with data stored across said at least two rows. Finally, the output signals are read out and a transformation operation is concurrently performed, in-memory, on the target values based on the operand values. This way transformed data are obtained by way of in-memory processing. The transformation may for instance be a cryptographic operation; the operand data may encode a cryptographic key. The invention is further directed to related apparatuses and systems, notably cryptographic service systems.

Abstract: A memory device enabling a reduced minimal conductance state may be provided. The device comprises a first electrode, a second electrode and phase-change material between the first electrode and the second electrode, wherein the phase-change material enables a plurality of conductivity states depending on the ratio between a crystalline and an amorphous phase of the phase-change material. The memory device comprises additionally a projection layer portion in a region between the first electrode and the second electrode. Thereby, an area directly covered by the phase-change material in the amorphous phase in a reset state of the memory device is larger than an area of the projection layer portion oriented to the phase-change material, such that a discontinuity in the conductance states of the memory device is created and a reduced minimal conductance state of the memory device in a reset state is enabled.

Abstract: A projected memory device includes a carbon-based projection component. The device includes two electrodes, a memory segment, and a projection component. The projection component and the memory segment form a dual element that connects the two electrodes. The projection component extends parallel to and in contact with the memory segment. The memory segment includes a resistive memory material, while the projection component includes a thin film of non-insulating material that essentially comprises carbon. In a particular implementation, the non-insulating material and the projection component essentially comprises amorphous carbon. Using carbon and, in particular, amorphous carbon, as a main component of the projection component, allows unprecedented flexibility to be achieved when tuning the electrical resistance of the projection component.

Abstract: A memory device enabling a reduced minimal conductance state may be provided. The device comprises a first electrode, a second electrode and phase-change material between the first electrode and the second electrode, wherein the phase-change material enables a plurality of conductivity states depending on the ratio between a crystalline and an amorphous phase of the phase-change material. The memory device comprises additionally a projection layer portion in a region between the first electrode and the second electrode. Thereby, an area directly covered by the phase-change material in the amorphous phase in a reset state of the memory device is larger than an area of the projection layer portion oriented to the phase-change material, such that a discontinuity in the conductance states of the memory device is created and a reduced minimal conductance state of the memory device in a reset state is enabled.

Abstract: A projected memory device includes a carbon-based projection component. The device includes two electrodes, a memory segment, and a projection component. The projection component and the memory segment form a dual element that connects the two electrodes. The projection component extends parallel to and in contact with the memory segment. The memory segment includes a resistive memory material, while the projection component includes a thin film of non-insulating material that essentially comprises carbon. In a particular implementation, the non-insulating material and the projection component essentially comprises amorphous carbon. Using carbon and, in particular, amorphous carbon, as a main component of the projection component, allows unprecedented flexibility to be achieved when tuning the electrical resistance of the projection component.

Abstract: A projected memory device includes a carbon-based projection component. The device includes two electrodes, a memory segment, and a projection component. The projection component and the memory segment form a dual element that connects the two electrodes. The projection component extends parallel to and in contact with the memory segment. The memory segment includes a resistive memory material, while the projection component includes a thin film of non-insulating material that essentially comprises carbon. In a particular implementation, the non-insulating material and the projection component essentially comprises amorphous carbon. Using carbon and, in particular, amorphous carbon, as a main component of the projection component, allows unprecedented flexibility to be achieved when tuning the electrical resistance of the projection component.

Abstract: A projected memory device includes a carbon-based projection component. The device includes two electrodes, a memory segment, and a projection component. The projection component and the memory segment form a dual element that connects the two electrodes. The projection component extends parallel to and in contact with the memory segment. The memory segment includes a resistive memory material, while the projection component includes a thin film of non-insulating material that essentially comprises carbon. In a particular implementation, the non-insulating material and the projection component essentially comprises amorphous carbon. Using carbon and, in particular, amorphous carbon, as a main component of the projection component, allows unprecedented flexibility to be achieved when tuning the electrical resistance of the projection component.

Abstract: The present disclosure relates to an apparatus for a memristor crossbar array. The apparatus comprises an adjustment circuit configured for receiving a current that is output by the array at an actual operating condition of the array. The apparatus further comprises a calibration circuit configured for determining a measured or modelled variation of output currents of the array at the actual operating condition with respect to a reference operating condition, wherein the adjustment circuit is configured to adjust the output current by the variation.

Abstract: The present disclosure relates to an apparatus for a memristor crossbar array. The apparatus comprises an adjustment circuit configured for receiving a current that is output by the array at an actual operating condition of the array. The apparatus further comprises a calibration circuit configured for determining a measured or modelled variation of output currents of the array at the actual operating condition with respect to a reference operating condition, wherein the adjustment circuit is configured to adjust the output current by the variation.

Abstract: Apparatus including: memory cell unit(s) having a variable-resistance channel component (CC) extending between first and second supply terminals for supplying read and write (R/W) signals to the unit in respective R/W modes, and resistive memory elements (RMEs) arranged along the CC, RME includes resistive memory material (RMM), extending along a respective channel segment (CHS) of the CC in contact therewith, in which respective lengths along that CHS of high- and low-resistance regions is variable in write mode, and a gate terminal provided on that CHS for controlling resistance of the CHS in response to control signal(s) (CS) applied to the gate terminal; and circuitry configured to apply the CS such that, in read mode, a RME(s) is selected by applying a CS producing CHS with resistance between the resistance regions of the RMM; and remaining RME(s) are deselected by applying CS producing CHS having resistance less than the low-resistance region.

Abstract: Apparatus including: memory cell unit(s) having a variable-resistance channel component (CC) extending between first and second supply terminals for supplying read and write (R/W) signals to the unit in respective R/W modes, and resistive memory elements (RMEs) arranged along the CC, RME includes resistive memory material (RMM), extending along a respective channel segment (CHS) of the CC in contact therewith, in which respective lengths along that CHS of high- and low-resistance regions is variable in write mode, and a gate terminal provided on that CHS for controlling resistance of the CHS in response to control signal(s) (CS) applied to the gate terminal; and circuitry configured to apply the CS such that, in read mode, a RME(s) is selected by applying a CS producing CHS with resistance between the resistance regions of the RMM; and remaining RME(s) are deselected by applying CS producing CHS having resistance less than the low-resistance region.

Abstract: Apparatus including: memory cell unit(s) having a variable-resistance channel component (CC) extending between first and second supply terminals for supplying read and write (R/W) signals to the unit in respective R/W modes, and resistive memory elements (RMEs) arranged along the CC, RME includes resistive memory material (RMM), extending along a respective channel segment (CHS) of the CC in contact therewith, in which respective lengths along that CHS of high- and low-resistance regions is variable in write mode, and a gate terminal provided on that CHS for controlling resistance of the CHS in response to control signal(s) (CS) applied to the gate terminal; and circuitry configured to apply the CS such that, in read mode, a RME(s) is selected by applying a CS producing CHS with resistance between the resistance regions of the RMM; and remaining RME(s) are deselected by applying CS producing CHS having resistance less than the low-resistance region.

Abstract: A memory device includes a plurality of memory cells and a control unit. The memory cells include a first segment including a resistive memory material for storing information in a plurality of resistance states, a second segment including a non-insulating material, a first terminal, a second terminal, and a third terminal. The first segment and the second segment are arranged in parallel between the first terminal and the second terminal. The control unit is configured to apply in a write mode a write voltage to the first and the second terminal for writing the resistance state, and to apply in a read mode a read voltage to the first and the second terminal for reading the resistance state, and to apply a control signal to the third terminal for adjusting the electrical resistance of the second segment. A related method and control unit are also disclosed.

Abstract: A tape head, adapted for reading and/or writing to a magnetic tape, has a tape-bearing surface and is configured to urge a magnetic tape against the bearing surface, in operation. The bearing surface includes a transducer area, having at least one transducer that is a read and/or write element, designed for reading and/or writing to a magnetic tape, and a structured area adjacent to the transducer area, comprising a periodic array of topographic features, the topographic features configured within the structured area to determine a minimal distance between the transducer area and a tape.

Abstract: A tape head, adapted for reading and/or writing to a magnetic tape, has a tape-bearing surface and is configured to urge a magnetic tape against the bearing surface, in operation. The bearing surface includes a transducer area, having at least one transducer that is a read and/or write element, designed for reading and/or writing to a magnetic tape, and a structured area adjacent to the transducer area, comprising a periodic array of topographic features, the topographic features configured within the structured area to determine a minimal distance between the transducer area and a tape.

Abstract: A tape head, adapted for reading and/or writing to a magnetic tape, has a tape-bearing surface and is configured to urge a magnetic tape against the bearing surface, in operation. The bearing surface includes a transducer area, having at least one transducer that is a read and/or write element, designed for reading and/or writing to a magnetic tape, and a structured area adjacent to the transducer area, comprising a periodic array of topographic features, the topographic features configured within the structured area to determine a minimal distance between the transducer area and a tape.