Patents by Inventor Varadarajan Devnath

Varadarajan Devnath has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12632617
    Abstract: A digital twin service of a provider network allows a user to build a digital twin to simulate behavior and changes of a physical system at a client's site. The digital twin service may receive, from the user, a definition for each model to be used to simulate each component of the physical system. For example, the user may indicate various properties of the model, behaviors of the model, and relationships between the model and one or more other models (e.g., chaining via inputs/outputs). The digital twin service may then build and deploy the models to a runtime environment. The runtime environment executes the models and receives telemetry data from the physical system. The user may modify the simulation (e.g., provide new telemetry data or modify/add new models). The simulation generates one or more results based on the modification and sends the results to a destination.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: May 19, 2026
    Assignee: Amazon Technologies, Inc
    Inventors: Palani Chinnakannan, Arvind Karuppasamy, Varadarajan Devnath
  • Publication number: 20260087202
    Abstract: A digital twin service of a provider network allows a user to build high fidelity models (“digital twins”) for components and for systems of multiple components. For a given component, the digital twin service receives, from a user, identification of interactions for the component (e.g., inputs/outputs at the boundary), identification of data sources at the system (e.g., sensor that stream data), and/or a definition of behavior of the component (e.g., one or more behavior functions to simulate the component). The digital twin service builds a digital twin model of the component based at least on the interactions, the data sources, and the behavior. The digital twin service may also receive, from the user, an indication to bind one or more outputs of the digital twin model to one or more inputs of at least another of the digital twin models to build a digital twin model of the system.
    Type: Application
    Filed: December 2, 2025
    Publication date: March 26, 2026
    Applicant: Amazon Technologies, Inc.
    Inventors: Palani Chinnakannan, Arvind Karuppasamy, Varadarajan Devnath
  • Patent number: 12511454
    Abstract: A digital twin service of a provider network allows a user to build high fidelity models (“digital twins”) for components and for systems of multiple components. For a given component, the digital twin service receives, from a user, identification of interactions for the component (e.g., inputs/outputs at the boundary), identification of data sources at the system (e.g., sensor that stream data), and/or a definition of behavior of the component (e.g., one or more behavior functions to simulate the component). The digital twin service builds a digital twin model of the component based at least on the interactions, the data sources, and the behavior. The digital twin service may also receive, from the user, an indication to bind one or more outputs of the digital twin model to one or more inputs of at least another of the digital twin models to build a digital twin model of the system.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: December 30, 2025
    Assignee: Amazon Technologies, Inc.
    Inventors: Palani Chinnakannan, Arvind Karuppasamy, Varadarajan Devnath
  • Patent number: 7869388
    Abstract: A method and apparatus for a Gigabit Ethernet transceiver that has a Class-B amplifier in a main transmitter for higher efficiency and power handling capabilities. The output current of the main transmitter is produced by a reference voltage applied across a resistor, where the reference voltage generator, resistor and amplifier are fabricated on the same substrate, such that the output current is constant across process voltage and temperature. The transceiver also has a replica transmitter whose signal is used to cancel the main transmitter signal at the input of the receiver section of the transceiver. The replica transmitter is fabricated on the same substrate as the main transmitter, such that its output signal reflects non-linearities in the main transmitter across process voltage and temperature.
    Type: Grant
    Filed: May 26, 2010
    Date of Patent: January 11, 2011
    Assignee: National Semiconductor Corporation
    Inventors: Ramsin Michael Ziazadeh, Varadarajan Devnath
  • Publication number: 20100238848
    Abstract: A method and apparatus for a Gigabit Ethernet transceiver that has a Class-B amplifier in a main transmitter for higher efficiency and power handling capabilities. The output current of the main transmitter is produced by a reference voltage applied across a resistor, where the reference voltage generator, resistor and amplifier are fabricated on the same substrate, such that the output current is constant across process voltage and temperature. The transceiver also has a replica transmitter whose signal is used to cancel the main transmitter signal at the input of the receiver section of the transceiver. The replica transmitter is fabricated on the same substrate as the main transmitter, such that its output signal reflects non-linearities in the main transmitter across process voltage and temperature.
    Type: Application
    Filed: May 26, 2010
    Publication date: September 23, 2010
    Applicant: NATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Ramsin Michael Ziazadeh, Varadarajan Devnath
  • Patent number: 7729300
    Abstract: A method and apparatus for a Gigabit Ethernet transceiver that has a Class-B amplifier in a main transmitter for higher efficiency and power handling capabilities. The output current of the main transmitter is produced by a reference voltage applied across a resistor, where the reference voltage generator, resistor and amplifier are fabricated on the same substrate, such that the output current is constant across process voltage and temperature. The transceiver also has a replica transmitter whose signal is used to cancel the main transmitter signal at the input of the receiver section of the transceiver. The replica transmitter is fabricated on the same substrate as the main transmitter, such that its output signal reflects non-linearities in the main transmitter across process voltage and temperature.
    Type: Grant
    Filed: August 19, 2005
    Date of Patent: June 1, 2010
    Assignee: National Semiconductor Corporation
    Inventors: Ramsin Michael Ziazadeh, Varadarajan Devnath
  • Patent number: 7454647
    Abstract: A skew measurement system and method wherein each of the signals among which the skew is to be determined is connected one at a time to a clock recovery loop. The locked state of the clock recovery loop is used as an indicator of the skew of the data signal relative to the internal clock of the clock recovery loop. By measuring the difference between the locked state of different signals, their relative skew can be measured.
    Type: Grant
    Filed: July 28, 2005
    Date of Patent: November 18, 2008
    Assignee: National Semiconductor Corporation
    Inventors: Varadarajan Devnath, Vijaya Ceekala, James B. Wieser, Lawrence K. Whitcomb
  • Patent number: 7307458
    Abstract: A serial communication interface driver is provided wherein current steering switches are also used to provide termination impedances. The output voltage can be produced by a voltage-dividing current path between two regulated voltages, which provides improved efficiency.
    Type: Grant
    Filed: May 27, 2005
    Date of Patent: December 11, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Alan E. Segervall, Vijaya Ceekala, Varadarajan Devnath, James B. Wieser
  • Patent number: 7301366
    Abstract: A tunable impedance circuit is provided wherein at least one of a plurality of impedance elements is combined with at least another of the plurality of impedance elements to produce a composite impedance. A control voltage is used to determine how many of the impedance elements are to be combined to produce the composite impedance. A current that is substantially invariant over a range of operating conditions is caused to flow through a control impedance to produce the control voltage.
    Type: Grant
    Filed: June 17, 2005
    Date of Patent: November 27, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Varadarajan Devnath, Alan E. Segervall
  • Patent number: 7285978
    Abstract: An H-bridge LVDS driver circuit includes a means to calibrate the output impedance of the switches of an LVDS driver to any desired value.
    Type: Grant
    Filed: July 15, 2005
    Date of Patent: October 23, 2007
    Assignee: National Semiconductor Corporation
    Inventor: Varadarajan Devnath
  • Patent number: 7135902
    Abstract: Integrated differential data signal generator circuitry for providing differential data signals with controlled rise and fall times and built-in test capabilities.
    Type: Grant
    Filed: April 22, 2005
    Date of Patent: November 14, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Ramsin M. Ziazadeh, Varadarajan Devnath
  • Patent number: 6970048
    Abstract: A circuit and method for generating quadrature signals with a deterministic phase relationship. Between two inductive-capacitive (LC) based quadrature voltage controlled oscillators (VCO), phase shift circuitry is interposed such that the individual LC VCO circuits produce signals with corresponding phase delays which ensure that the desired lead or lag phase relationship between the quadrature signals is achieved.
    Type: Grant
    Filed: December 12, 2003
    Date of Patent: November 29, 2005
    Assignee: National Semiconductor Corporation
    Inventors: Varadarajan Devnath, Jitendra Mohan, Quyet Nguyen, Yongseon Koh
  • Patent number: 6956439
    Abstract: A transimpedance amplifier with controllable noise reduction in which DC offsets due to the input signal are tolerated during reception of low input signals by reducing, e.g., terminating, a compensation current to remove a dominant source of thermal noise, but compensated during reception of higher input signals where the effects of DC offsets are more dominant.
    Type: Grant
    Filed: December 12, 2003
    Date of Patent: October 18, 2005
    Assignee: National Semiconductor Corporation
    Inventor: Varadarajan Devnath
  • Patent number: 6762625
    Abstract: A programmable differential current mode line driver with multiple classes of circuit operation that can be digitally programmed to operate in a low distortion, low noise class A mode or a low power class B mode, with multiple signal levels available in each mode of operation.
    Type: Grant
    Filed: November 25, 2002
    Date of Patent: July 13, 2004
    Assignee: National Semiconductor Corporation
    Inventor: Varadarajan Devnath