Patents by Inventor Varistha Chobpattana

Varistha Chobpattana has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • High capacitance density gate dielectrics for III-V semiconductor channels using a pre-disposition surface treatment involving plasma and TI precursor exposure
    Patent number: 9190266
    Abstract: A method of depositing a uniform dielectric thin film is provided that includes pre-cleaning a substrate surface, using a deposition apparatus, by exposing the substrate to a plasma, where the plasma can include a nitrogen plasma, a hydrogen plasma, an ammonia plasma, or a plasma containing nitrogen-hydrogen radicals in a plasma chamber of the deposition apparatus, where the substrate comprises a semiconductor of type III-V, and exposing the pre-cleaned substrate surface, using the deposition apparatus, to alternating cycles of the plasma, using the plasma chamber, and pulses of a precursor containing Ti, using a deposition chamber of the deposition apparatus, where less than 10% TiN or Ti—O—N bonding is present on said substrate surface, where a uniform substantially TiO2 dielectric thin film is formed on said substrate.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: November 17, 2015
    Assignee: The Regents of the University of California
    Inventors: Susanne Stemmer, Varistha Chobpattana