Abstract: A configurable integrated circuit includes a first register having N EPROM cells, and a second register having N EPROM cells, each EPROM cell in the second register corresponding to a distinct one of the N EPROM cells in the first register. Register programming circuits store a set of N binary configuration values in the first register and store boolean complements of the N binary configuration values in the second register. N configuration value sensing circuits are used to read the EPROM cells and generate N configuration signals. Each configuration value sensing circuit is a set/reset latch coupled to one EPROM cell in the first register and the corresponding EPROM cell in the second register. Under normal operating conditions, the latch generates a configuration signal corresponding to the configuration value stored in the one EPROM cell in the first register.

Abstract: A memory array such as an EPROM device includes circuitry that permits testing of a I/O portion of the device without writing data to the EPROM. A data program block that applies a data dependent high voltage pulse to a selected column line for programming can be set to programming or test mode. In the normal, or programming mode, the data input to the data program block is output to the EPROM memory array as is normally required to write to the device. In the test mode, the data output from the data program block controllably connects or decouples the array input line to ground depending upon a binary state of the the input signal. A test output is evaluated using the same sense amp used to evaluate data read from a memory cells of the EPROM array during normal read operations. To prevent writing to the memory cells of the memory array during test, the programming voltage supply is prevented from being applied to a selected column line and all rows in the memory array are deselected simultaneously.

Abstract: Architecture for a memory device and a method for employing the architecture for testing of the memory device are provided. In a memory device such as a one-time programmable EPROM, an extra row and an extra column of memory cells are added to the regular array. The extra column is configured so that, during a first test configuration, a sense device connected to the column line of the extra column of cells will detect whether exactly one row line of the correct parity is selected in response to input of a row address. Similarly, the extra row is configured so that the sense amp connected to the column lines of the regular array, can determine whether exactly one column line of the correct parity from the regular array is selected in response to input of a column address. The row decoder and row address lines are tested separately from the testing of the column decoder and column address lines.