Patents by Inventor Varsha Apte

Varsha Apte has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Technologies for network application programming with field-programmable gate arrays
    Patent number: 10268464
    Abstract: Technologies for network application programming include a computing device that analyzes a network application source program. The source program includes a declarative description of a network application in a domain-specific language, such as P4. The computing device translates the declarative description of the network application into a register-transfer level (RTL) description, and then compiles the RTL description into a bitstream definition that is targeted to an FPGA. For example, the computing device may generate a parse graph based on the network application source program, and then generate an RTL TCAM-SRAM structure for each node of the parse graph. The computing device may optimize the RTL description, for example by simplifying RTL structures or removing unused logic. The computing device may program an FPGA with the bitstream definition. Other embodiments are described and claimed.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: April 23, 2019
    Assignee: Intel Corporation
    Inventors: Daniel P. Daly, Thomas E. Willis, Pat Wang, Vishal Anand, Hung Nguyen, Varsha Apte
  • TECHNOLOGIES FOR NETWORK APPLICATION PROGRAMMING WITH FIELD-PROGRAMMABLE GATE ARRAYS
    Publication number: 20190012156
    Abstract: Technologies for network application programming include a computing device that analyzes a network application source program. The source program includes a declarative description of a network application in a domain-specific language, such as P4. The computing device translates the declarative description of the network application into a register-transfer level (RTL) description, and then compiles the RTL description into a bitstream definition that is targeted to an FPGA. For example, the computing device may generate a parse graph based on the network application source program, and then generate an RTL TCAM-SRAM structure for each node of the parse graph. The computing device may optimize the RTL description, for example by simplifying RTL structures or removing unused logic. The computing device may program an FPGA with the bitstream definition. Other embodiments are described and claimed.
    Type: Application
    Filed: July 7, 2017
    Publication date: January 10, 2019
    Inventors: Daniel P. Daly, Thomas E. Willis, Pat Wang, Vishal Anand, Hung Nguyen, Varsha Apte