Patents by Inventor Varun Agrawal

Varun Agrawal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250110861
    Abstract: In accordance with the described techniques for data compression using reconfigurable hardware based on data redundancy patterns, a computing device includes a memory, processing-in-memory units, a host processing unit, and a compression unit having reconfigurable logic for performing multiple compression algorithms. The host processing unit issues processing-in-memory requests instructing the processing-in-memory units to scan a block of the memory for one or more data redundancy patterns, and to identify a compression algorithm of the multiple compression algorithms based on the one or more data redundancy patterns. Further, the host processing unit issues a memory request to access a memory address in the block of the memory. The memory request causes data of the memory address to be communicated from the block of the memory to the compression unit to be compressed using the compression algorithm.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Moumita Dey, Varun Agrawal
  • Publication number: 20250042436
    Abstract: Techniques are described herein for safely transitioning a vehicle from a first trajectory to a second trajectory. In response to a safety event, for example, a vehicle may switch from being controlled in accordance with a nominal planner output (a planned trajectory) to a safety, or stopping, trajectory. In some examples, in response to the vehicle overcoming the safety event, a safe and smooth return to a nominal planning system output trajectory (an updated planned trajectory) may be determined and used to cause the vehicle to continue along to a previously determined destination.
    Type: Application
    Filed: July 31, 2023
    Publication date: February 6, 2025
    Inventors: Varun AGRAWAL, Brian Michael FILARSKY, Joseph FUNKE, Vincent Andreas LAURENSE, Glenn Xavier LIEM, Jiayin XIA
  • Publication number: 20250002047
    Abstract: Techniques for optimal trajectory generation for a vehicle are described herein. In some cases, the techniques described herein include determining a first primary trajectory by a first component (e.g., a planner component) of the vehicle, determining a triggering event associated with the first primary trajectory by a second component (e.g., a trajectory validation component) of the vehicle, controlling the vehicle based on an alternative trajectory (e.g., a trajectory configured to cause the vehicle to stop and/or slow down) in response to the triggering event, determining a second primary trajectory by the first component and based at least in part on a state of the vehicle along the alternative trajectory, and one or more of: (i) controlling the vehicle based on the alternative trajectory if the triggering event is still present, or (ii) controlling the vehicle based on the second primary trajectory if the triggering event is no longer present.
    Type: Application
    Filed: June 30, 2023
    Publication date: January 2, 2025
    Applicant: Zoox, Inc.
    Inventors: Vincent Andreas Laurense, Glenn Xavier Liem, Joseph Funke, Varun Agrawal, Jiayin Xia
  • Patent number: 12175073
    Abstract: Systems, apparatuses, and methods for reusing remote registers in processing in memory (PIM) are disclosed. A system includes at least a host processor, a memory controller, and a PIM device. When the memory controller receives, from the host processor, an operation targeting the PIM device, the memory controller determines whether an optimization can be applied to the operation. The memory controller converts the operation into N PIM commands if the optimization is not applicable. Otherwise, the memory controller converts the operation into a N?1 PIM commands if the optimization is applicable. For example, if the operation involves reusing a constant value, a copy command can be omitted, resulting in memory bandwidth reduction and power consumption savings. In one scenario, the memory controller includes a constant-value cache, and the memory controller performs a lookup of the constant-value cache to determine if the optimization is applicable for a given operation.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: December 24, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: John Kalamatianos, Varun Agrawal, Niti Madan
  • Publication number: 20240326791
    Abstract: Techniques for determining an optimal trajectory for a vehicle are discussed herein. In some cases, the described techniques include receiving, from a first computing system and by a second computing system (e.g., a computing system associated with a trajectory validation system of the vehicle), a primary trajectory and an alternative trajectory for the vehicle. In some cases, the second computing system is configured to select or otherwise determine whether to select the primary trajectory, the alternative trajectory, or neither trajectory for the vehicle. In some cases, the alternative trajectory is determined by applying a lateral swerve to the primary trajectory.
    Type: Application
    Filed: March 30, 2023
    Publication date: October 3, 2024
    Applicant: Zoox, Inc.
    Inventors: Taylor Scott Clawson, Olivier Amaury Toupet, Varun Agrawal, Leonardo Poubel Orenstein, Jonathan Scott Mcneely
  • Publication number: 20240330186
    Abstract: Cache directory lookup address augmentation techniques are described. In one example, a system includes a cache system including a plurality of cache levels and a cache coherence controller. The cache coherence controller is configured to perform a cache directory lookup using a cache directory. The cache directory lookup is configured to indicate whether data associated with a memory address specified by a memory request is valid in memory. The cache directory lookup is augmented to include an additional memory address based on the memory address.
    Type: Application
    Filed: March 30, 2023
    Publication date: October 3, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Travis Henry Boraten, Varun Agrawal
  • Patent number: 12075974
    Abstract: A surgical robotic system includes an endoscope, a robotic arm including a drive mechanism, the drive mechanism coupled to the endoscope. The surgical robotic system further includes a controller configured to receive a command to move the endoscope using the robotic arm, access a set of calibration parameters associated with the endoscope, generate an adjusted command based on the command and the set of calibration parameters, and provide the adjusted command to the robotic arm to move the endoscope.
    Type: Grant
    Filed: October 7, 2021
    Date of Patent: September 3, 2024
    Assignee: Auris Health, Inc.
    Inventors: Varun Agrawal, Atiyeh Ghoreyshi, David S. Mintz
  • Patent number: 12026401
    Abstract: In accordance with described techniques for DRAM row management for processing in memory, a plurality of instructions are obtained for execution by a processing in memory component embedded in a dynamic random access memory. An instruction is identified that last accesses a row of the dynamic random access memory, and a subsequent instruction is identified that first accesses an additional row of the dynamic random access memory. A first command is issued to close the row and a second command is issued to open the additional row after the row is last accessed by the instruction.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: July 2, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Niti Madan, Yasuko Eckert, Varun Agrawal, John Kalamatianos
  • Publication number: 20240211402
    Abstract: In accordance with the described techniques for condensed coherence directory entries for processing in memory, a computing device includes a core that includes a cache, a memory that includes multiple banks, a coherence directory that includes a condensed entry indicating that data associated with a memory address and the multiple banks is not stored in the cache, and a cache coherence controller. The cache coherence controller receives a processing-in-memory command to the memory address and performs a single lookup in the coherence directory for the processing-in-memory command based on inclusion of the condensed entry in the coherence directory.
    Type: Application
    Filed: December 27, 2022
    Publication date: June 27, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Travis Henry Boraten, Varun Agrawal, Michael Warren Boyer
  • Patent number: 12008378
    Abstract: A parallel processing (PP) level coherence directory, also referred to as a Processing In-Memory Probe Filter (PimPF), is added to a coherence directory controller. When the coherence directory controller receives a broadcast PIM command from a host, or a PIM command that is directed to multiple memory banks in parallel, the PimPF accelerates processing of the PIM command by maintaining a directory for cache coherence that is separate from existing system level directories in the coherence directory controller. The PimPF maintains a directory according to address signatures that define the memory addresses affected by a broadcast PIM command. Two implementations are described: a lightweight implementation that accelerates PIM loads into registers, and a heavyweight implementation that accelerates both PIM loads into registers and PIM stores into memory.
    Type: Grant
    Filed: April 10, 2023
    Date of Patent: June 11, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Varun Agrawal, Yasuko Eckert
  • Publication number: 20240092350
    Abstract: Techniques for validating or determining trajectories for a vehicle are discussed herein. A trajectory management component can receive status and/or error data from other safety system components and select or otherwise determine safe and valid vehicle trajectories. A perception component of a safety system can validate a trajectory upon which the trajectory management component can wait for selecting a vehicle trajectory, validate trajectories stored in a queue, and/or utilize kinematics for validation of trajectories. A filter component of the safety system can filter out objects based on trajectories stored in a queue. A collision detection component of the safety system can determine the collision states based on trajectories stored in a queue or determine a collision state upon which the trajectory management component can wait for selecting or otherwise determining a vehicle trajectory.
    Type: Application
    Filed: June 16, 2022
    Publication date: March 21, 2024
    Inventors: Varun Agrawal, Taylor Scott Clawson, Gareth John Ellis, Brian Michael Filarsky, Giacomo Zavolta Taylor
  • Publication number: 20240034308
    Abstract: Systems and techniques for determining a trajectory for use in controlling a vehicle are described. A trajectory determination system may generate a variety of trajectories for potential use in controlling a vehicle, including a maximum braking trajectory that enables the maximum application of the vehicle's brakes. A vehicle computing system may determine a distance between vehicle and an obstacle and stopping distances for the various trajectories and implement the maximum braking trajectory after determining that the distance to stop for that trajectory is the same as, but not substantially greater than, the distance between the vehicle and the obstacle.
    Type: Application
    Filed: July 29, 2022
    Publication date: February 1, 2024
    Inventors: Varun Agrawal, Jacob Daniel Boydston, Taylor Scott Clawson, Joshua Dean Egbert, Brian Michael Filarsky, Joseph Funke, Noureldin Ehab Hendy, Richard Hsieh, Glenn Xavier Liem, David Benjamin Lu, Leonardo Poubel Orenstein
  • Publication number: 20240004584
    Abstract: In accordance with described techniques for DRAM row management for processing in memory, a plurality of instructions are obtained for execution by a processing in memory component embedded in a dynamic random access memory. An instruction is identified that last accesses a row of the dynamic random access memory, and a subsequent instruction is identified that first accesses an additional row of the dynamic random access memory. A first command is issued to close the row and a second command is issued to open the additional row after the row is last accessed by the instruction.
    Type: Application
    Filed: June 30, 2022
    Publication date: January 4, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Niti Madan, Yasuko Eckert, Varun Agrawal, John Kalamatianos
  • Publication number: 20240004369
    Abstract: Systems and methods of providing a haptic barrier for an instrument include a computer-assisted device. The computer-assisted device includes a grip input control, a repositionable arm configured to support an instrument, and one or more processors. The one or more processors are configured to detect a position of the grip input control in a first direction of a degree of freedom having In a first region, a second region, and a third region between the first and second regions; in response to determining that the detected position is in the first region, operate the instrument according to a first mode; in response to determining that the detected position is in the third region, provide a haptic barrier to resist movement of the grip input control through the third region; and in response to determining that the detected position is in the second region, operate the instrument according to a second mode.
    Type: Application
    Filed: November 30, 2021
    Publication date: January 4, 2024
    Inventors: Varun AGRAWAL, Hsien-Hsin LIAO, Angel Jeremy PEREZ ROSILLO, Korissa A. REYES, Lawton N. VERNER, Keith J. WATZA
  • Publication number: 20230244496
    Abstract: A parallel processing (PP) level coherence directory, also referred to as a Processing In-Memory Probe Filter (PimPF), is added to a coherence directory controller. When the coherence directory controller receives a broadcast PIM command from a host, or a PIM command that is directed to multiple memory banks in parallel, the PimPF accelerates processing of the PIM command by maintaining a directory for cache coherence that is separate from existing system level directories in the coherence directory controller. The PimPF maintains a directory according to address signatures that define the memory addresses affected by a broadcast PIM command. Two implementations are described: a lightweight implementation that accelerates PIM loads into registers, and a heavyweight implementation that accelerates both PIM loads into registers and PIM stores into memory.
    Type: Application
    Filed: April 10, 2023
    Publication date: August 3, 2023
    Inventors: Varun Agrawal, Yasuko Eckert
  • Patent number: 11625251
    Abstract: A parallel processing (PP) level coherence directory, also referred to as a Processing In-Memory Probe Filter (PimPF), is added to a coherence directory controller. When the coherence directory controller receives a broadcast PIM command from a host, or a PIM command that is directed to multiple memory banks in parallel, the PimPF accelerates processing of the PIM command by maintaining a directory for cache coherence that is separate from existing system level directories in the coherence directory controller. The PimPF maintains a directory according to address signatures that define the memory addresses affected by a broadcast PIM command. Two implementations are described: a lightweight implementation that accelerates PIM loads into registers, and a heavyweight implementation that accelerates both PIM loads into registers and PIM stores into memory.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: April 11, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Varun Agrawal, Yasuko Eckert
  • Publication number: 20230030708
    Abstract: A method for capturing an object in a cavity in a patient is described. The method includes advancing a ureteroscope into the cavity containing the object. A basket is advanced through a working channel of the ureteroscope. The basket is opened within the cavity and is positioned so as to enclose the object. Then, two actions are performed simultaneously. The basket is collapsed while simultaneously the basket tool is advanced forward so that the object remains within the basket, ideally near the center of the basket, as the basket closes around the object. Once the object is captured, the basket is retracted to remove the object out of the cavity. Further, this process may be automated by having the method carried out by robotic arms acting in tandem, with one or more robotic arms advancing the basket tool or ureteroscope, and another robotic arm collapsing the basket.
    Type: Application
    Filed: July 4, 2022
    Publication date: February 2, 2023
    Inventors: David P. Noonan, Joseph A. Urban, JR., Varun Agrawal
  • Patent number: 11550588
    Abstract: A branch predictor of a processor includes one or more prediction structures, including a predicted branch address and predicted branch direction, that identify predicted branches. To reduce power consumption, the branch predictor selects one or more of the prediction structures that are not expected to provide useful branch prediction information and filters the selected structures such that the filtered structures are not used for branch prediction. The branch predictor thereby reduces the amount of power used for branch prediction without substantially reducing the accuracy of the predicted branches.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: January 10, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: John Kalamatianos, Adithya Yalavarti, Varun Agrawal, Subhankar Pal, Vinesh Srinivasan
  • Patent number: 11442727
    Abstract: An electronic device includes a processor, a branch predictor in the processor, and a predictor controller in the processor. The branch predictor includes multiple prediction functional blocks, each prediction functional block configured for generating predictions for control transfer instructions (CTIs) in program code based on respective prediction information, the branch predictor configured to select, from among predictions generated by the prediction functional blocks for each CTI, a selected prediction to be used for that CTI. The predictor controller keeps a record of prediction functional blocks from which the branch predictor previously selected predictions for CTIs. The predictor controller uses information from the record for controlling which prediction functional blocks are used by the branch predictor for generating predictions for CTIs.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: September 13, 2022
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Varun Agrawal, John Kalamatianos
  • Patent number: 11382650
    Abstract: A method for capturing an object in a cavity in a patient is described. The method includes advancing a ureteroscope into the cavity containing the object. A basket is advanced through a working channel of the ureteroscope. The basket is opened within the cavity and is positioned so as to enclose the object. Then, two actions are performed simultaneously. The basket is collapsed while simultaneously the basket tool is advanced forward so that the object remains within the basket, ideally near the center of the basket, as the basket closes around the object. Once the object is captured, the basket is retracted to remove the object out of the cavity. Further, this process may be automated by having the method carried out by robotic arms acting in tandem, with one or more robotic arms advancing the basket tool or ureteroscope, and another robotic arm collapsing the basket.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: July 12, 2022
    Assignee: Auris Health, Inc.
    Inventors: David P. Noonan, Joseph A. Urban, Jr., Varun Agrawal