Abstract: In accordance with the described techniques for data compression using reconfigurable hardware based on data redundancy patterns, a computing device includes a memory, processing-in-memory units, a host processing unit, and a compression unit having reconfigurable logic for performing multiple compression algorithms. The host processing unit issues processing-in-memory requests instructing the processing-in-memory units to scan a block of the memory for one or more data redundancy patterns, and to identify a compression algorithm of the multiple compression algorithms based on the one or more data redundancy patterns. Further, the host processing unit issues a memory request to access a memory address in the block of the memory. The memory request causes data of the memory address to be communicated from the block of the memory to the compression unit to be compressed using the compression algorithm.

Abstract: A technique automatically identifies and resolves prohibited maneuvers in candidate routes generated by a routing system. Examples of prohibited maneuvers include traveling over a non-navigable path, traveling in an incorrect direction over a roadway, and an improper turn. The technique determines whether the candidate routes contain prohibited maneuvers by comparing the candidate routes with plural types of route-related validation data in plural respective validation processes. For example, a first validation process compares the candidate routes with a collection of GPS traces. A second validation process compares the candidate routes with map reference data. The technique further includes provisions for correcting the causes of identified prohibited maneuvers. Overall, the technique reduces the amount of manual effort involved in verifying the accuracy of routes produced by the routing system, and improves the accuracy, reliability, and safety of the routing system.

Abstract: Integrated application performance and infrastructure management is described. Performance of an application and utilization of provisioned infrastructure for supporting the application are proactively monitored. A determination is made that the application is not performing according to application dimensioning information or the provisioned infrastructure is being over utilized. In response to determining the provisioned infrastructure is being over utilized, an adjustment to the provisioned infrastructure to prevent over utilization is initiated. In response to determining the application is not performing according to the application dimensioning information, an alert indicating the application is not performing according to the application dimensioning information is generated. In response to the alert, the application dimensioning information is updated or the application is adjusted to perform according to the application dimensioning information.

Abstract: A method includes providing a neural network with metrics obtained from an execution of an application in a test environment to determine rule-related weights, scaling rule results with the rule-related weights to determine scaled rule results. The method also includes re-training the neural network with the rule results of the application, an indication that the executed application is selected for deployment in the production environment, and rule results of other applications in the test environment in response to a determination that the scaled rule results fail a threshold but that the application is selected for deployment in a production environment. The method also includes providing the re-trained neural network with the rule results to generate updated rule-related weights and scaling the rule results by the updated rule-related weights to determine updated scaled rule results.

Abstract: Techniques are described herein for safely transitioning a vehicle from a first trajectory to a second trajectory. In response to a safety event, for example, a vehicle may switch from being controlled in accordance with a nominal planner output (a planned trajectory) to a safety, or stopping, trajectory. In some examples, in response to the vehicle overcoming the safety event, a safe and smooth return to a nominal planning system output trajectory (an updated planned trajectory) may be determined and used to cause the vehicle to continue along to a previously determined destination.

Abstract: Techniques for optimal trajectory generation for a vehicle are described herein. In some cases, the techniques described herein include determining a first primary trajectory by a first component (e.g., a planner component) of the vehicle, determining a triggering event associated with the first primary trajectory by a second component (e.g., a trajectory validation component) of the vehicle, controlling the vehicle based on an alternative trajectory (e.g., a trajectory configured to cause the vehicle to stop and/or slow down) in response to the triggering event, determining a second primary trajectory by the first component and based at least in part on a state of the vehicle along the alternative trajectory, and one or more of: (i) controlling the vehicle based on the alternative trajectory if the triggering event is still present, or (ii) controlling the vehicle based on the second primary trajectory if the triggering event is no longer present.

Abstract: Systems, apparatuses, and methods for reusing remote registers in processing in memory (PIM) are disclosed. A system includes at least a host processor, a memory controller, and a PIM device. When the memory controller receives, from the host processor, an operation targeting the PIM device, the memory controller determines whether an optimization can be applied to the operation. The memory controller converts the operation into N PIM commands if the optimization is not applicable. Otherwise, the memory controller converts the operation into a N?1 PIM commands if the optimization is applicable. For example, if the operation involves reusing a constant value, a copy command can be omitted, resulting in memory bandwidth reduction and power consumption savings. In one scenario, the memory controller includes a constant-value cache, and the memory controller performs a lookup of the constant-value cache to determine if the optimization is applicable for a given operation.

Abstract: Cache directory lookup address augmentation techniques are described. In one example, a system includes a cache system including a plurality of cache levels and a cache coherence controller. The cache coherence controller is configured to perform a cache directory lookup using a cache directory. The cache directory lookup is configured to indicate whether data associated with a memory address specified by a memory request is valid in memory. The cache directory lookup is augmented to include an additional memory address based on the memory address.

Abstract: Techniques for determining an optimal trajectory for a vehicle are discussed herein. In some cases, the described techniques include receiving, from a first computing system and by a second computing system (e.g., a computing system associated with a trajectory validation system of the vehicle), a primary trajectory and an alternative trajectory for the vehicle. In some cases, the second computing system is configured to select or otherwise determine whether to select the primary trajectory, the alternative trajectory, or neither trajectory for the vehicle. In some cases, the alternative trajectory is determined by applying a lateral swerve to the primary trajectory.

Abstract: A surgical robotic system includes an endoscope, a robotic arm including a drive mechanism, the drive mechanism coupled to the endoscope. The surgical robotic system further includes a controller configured to receive a command to move the endoscope using the robotic arm, access a set of calibration parameters associated with the endoscope, generate an adjusted command based on the command and the set of calibration parameters, and provide the adjusted command to the robotic arm to move the endoscope.

Abstract: In accordance with described techniques for DRAM row management for processing in memory, a plurality of instructions are obtained for execution by a processing in memory component embedded in a dynamic random access memory. An instruction is identified that last accesses a row of the dynamic random access memory, and a subsequent instruction is identified that first accesses an additional row of the dynamic random access memory. A first command is issued to close the row and a second command is issued to open the additional row after the row is last accessed by the instruction.

Abstract: In accordance with the described techniques for condensed coherence directory entries for processing in memory, a computing device includes a core that includes a cache, a memory that includes multiple banks, a coherence directory that includes a condensed entry indicating that data associated with a memory address and the multiple banks is not stored in the cache, and a cache coherence controller. The cache coherence controller receives a processing-in-memory command to the memory address and performs a single lookup in the coherence directory for the processing-in-memory command based on inclusion of the condensed entry in the coherence directory.

Abstract: A parallel processing (PP) level coherence directory, also referred to as a Processing In-Memory Probe Filter (PimPF), is added to a coherence directory controller. When the coherence directory controller receives a broadcast PIM command from a host, or a PIM command that is directed to multiple memory banks in parallel, the PimPF accelerates processing of the PIM command by maintaining a directory for cache coherence that is separate from existing system level directories in the coherence directory controller. The PimPF maintains a directory according to address signatures that define the memory addresses affected by a broadcast PIM command. Two implementations are described: a lightweight implementation that accelerates PIM loads into registers, and a heavyweight implementation that accelerates both PIM loads into registers and PIM stores into memory.

Abstract: Techniques for validating or determining trajectories for a vehicle are discussed herein. A trajectory management component can receive status and/or error data from other safety system components and select or otherwise determine safe and valid vehicle trajectories. A perception component of a safety system can validate a trajectory upon which the trajectory management component can wait for selecting a vehicle trajectory, validate trajectories stored in a queue, and/or utilize kinematics for validation of trajectories. A filter component of the safety system can filter out objects based on trajectories stored in a queue. A collision detection component of the safety system can determine the collision states based on trajectories stored in a queue or determine a collision state upon which the trajectory management component can wait for selecting or otherwise determining a vehicle trajectory.

Abstract: Systems and techniques for determining a trajectory for use in controlling a vehicle are described. A trajectory determination system may generate a variety of trajectories for potential use in controlling a vehicle, including a maximum braking trajectory that enables the maximum application of the vehicle's brakes. A vehicle computing system may determine a distance between vehicle and an obstacle and stopping distances for the various trajectories and implement the maximum braking trajectory after determining that the distance to stop for that trajectory is the same as, but not substantially greater than, the distance between the vehicle and the obstacle.

Abstract: In accordance with described techniques for DRAM row management for processing in memory, a plurality of instructions are obtained for execution by a processing in memory component embedded in a dynamic random access memory. An instruction is identified that last accesses a row of the dynamic random access memory, and a subsequent instruction is identified that first accesses an additional row of the dynamic random access memory. A first command is issued to close the row and a second command is issued to open the additional row after the row is last accessed by the instruction.

Abstract: Systems and methods of providing a haptic barrier for an instrument include a computer-assisted device. The computer-assisted device includes a grip input control, a repositionable arm configured to support an instrument, and one or more processors. The one or more processors are configured to detect a position of the grip input control in a first direction of a degree of freedom having In a first region, a second region, and a third region between the first and second regions; in response to determining that the detected position is in the first region, operate the instrument according to a first mode; in response to determining that the detected position is in the third region, provide a haptic barrier to resist movement of the grip input control through the third region; and in response to determining that the detected position is in the second region, operate the instrument according to a second mode.

Abstract: A parallel processing (PP) level coherence directory, also referred to as a Processing In-Memory Probe Filter (PimPF), is added to a coherence directory controller. When the coherence directory controller receives a broadcast PIM command from a host, or a PIM command that is directed to multiple memory banks in parallel, the PimPF accelerates processing of the PIM command by maintaining a directory for cache coherence that is separate from existing system level directories in the coherence directory controller. The PimPF maintains a directory according to address signatures that define the memory addresses affected by a broadcast PIM command. Two implementations are described: a lightweight implementation that accelerates PIM loads into registers, and a heavyweight implementation that accelerates both PIM loads into registers and PIM stores into memory.

Abstract: A parallel processing (PP) level coherence directory, also referred to as a Processing In-Memory Probe Filter (PimPF), is added to a coherence directory controller. When the coherence directory controller receives a broadcast PIM command from a host, or a PIM command that is directed to multiple memory banks in parallel, the PimPF accelerates processing of the PIM command by maintaining a directory for cache coherence that is separate from existing system level directories in the coherence directory controller. The PimPF maintains a directory according to address signatures that define the memory addresses affected by a broadcast PIM command. Two implementations are described: a lightweight implementation that accelerates PIM loads into registers, and a heavyweight implementation that accelerates both PIM loads into registers and PIM stores into memory.

Abstract: A method for capturing an object in a cavity in a patient is described. The method includes advancing a ureteroscope into the cavity containing the object. A basket is advanced through a working channel of the ureteroscope. The basket is opened within the cavity and is positioned so as to enclose the object. Then, two actions are performed simultaneously. The basket is collapsed while simultaneously the basket tool is advanced forward so that the object remains within the basket, ideally near the center of the basket, as the basket closes around the object. Once the object is captured, the basket is retracted to remove the object out of the cavity. Further, this process may be automated by having the method carried out by robotic arms acting in tandem, with one or more robotic arms advancing the basket tool or ureteroscope, and another robotic arm collapsing the basket.