Patents by Inventor Varun JINDAL

Varun JINDAL has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Local staling parameter for cache memory management in a processor
    Patent number: 12632394
    Abstract: Aspects of the disclosure are directed to cache memory management. In accordance with one aspect, the disclosure includes a shared cache memory configured to store data into a plurality of cache lines; and a client coupled to the shared cache memory, the client configured to determine if a local staling state of one of the plurality of cache lines is inactive or active.
    Type: Grant
    Filed: January 31, 2024
    Date of Patent: May 19, 2026
    Assignee: QUALCOMM Incorporated
    Inventors: Varun Jindal, George Patsilaras, Vivekanandan Naveen
  • LOCAL STALING PARAMETER FOR CACHE MEMORY MANAGEMENT IN A PROCESSOR
    Publication number: 20250245169
    Abstract: Aspects of the disclosure are directed to cache memory management. In accordance with one aspect, the disclosure includes a shared cache memory configured to store data into a plurality of cache lines; and a client coupled to the shared cache memory, the client configured to determine if a local staling state of one of the plurality of cache lines is inactive or active.
    Type: Application
    Filed: January 31, 2024
    Publication date: July 31, 2025
    Inventors: Varun JINDAL, George PATSILARAS, Vivekanandan NAVEEN
  • Quality of service (QoS) control of processor applications
    Patent number: 12130773
    Abstract: Aspects of the disclosure are directed to a quality of service (QOS) assignment policy for processor applications in a system on a chip (SoC). In accordance with one aspect, the system on a chip (SoC) includes an applications central processing unit (CPU), wherein the applications CPU comprises a quality of service (QOS) database table configured to list a plurality of QoS metrics associated with a plurality of processor threads, wherein at least one of the plurality of QoS metrics is used to determine a dynamic clock and voltage scaling (DCVS) operating point; a graphics processing unit (GPU) coupled to the applications CPU; and a common interconnection databus coupled to the applications CPU and the GPU.
    Type: Grant
    Filed: December 19, 2022
    Date of Patent: October 29, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Bharat Kumar Rangarajan, Varun Jindal
  • QUALITY OF SERVICE (QOS) CONTROL OF PROCESSOR APPLICATIONS
    Publication number: 20240202159
    Abstract: Aspects of the disclosure are directed to a quality of service (QOS) assignment policy for processor applications in a system on a chip (SoC). In accordance with one aspect, the system on a chip (SoC) includes an applications central processing unit (CPU), wherein the applications CPU comprises a quality of service (QOS) database table configured to list a plurality of QoS metrics associated with a plurality of processor threads, wherein at least one of the plurality of QoS metrics is used to determine a dynamic clock and voltage scaling (DCVS) operating point; a graphics processing unit (GPU) coupled to the applications CPU; and a common interconnection databus coupled to the applications CPU and the GPU.
    Type: Application
    Filed: December 19, 2022
    Publication date: June 20, 2024
    Inventors: Bharat Kumar RANGARAJAN, Varun JINDAL