Patents by Inventor Varun Singh

Varun Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250123903
    Abstract: An example circuit, e.g., an integrated circuit, comprises processor cores, each of which includes multiple memory blocks; power control circuits respectively coupled to the processor cores; isolation circuits respectively coupled to the processor cores; and controller circuitry coupled to each of the processor cores, to each of the power control circuits, and to each of the isolation circuits. The controller circuitry is configured to select a subset of processor cores of the processor cores and a subset of memory blocks of the subset of processor cores for testing; and cause non-selected memory blocks of the processor cores to be at least one of power gated, clock gated, and isolated from the selected subset of memory blocks.
    Type: Application
    Filed: December 23, 2024
    Publication date: April 17, 2025
    Inventors: Devanathan VARADARAJAN, Varun SINGH, Jose Luis FLORES, Rejitha NAIR, David Matthew THOMPSON
  • Patent number: 12259789
    Abstract: One example includes an integrated circuit (IC). The IC includes non-volatile memory and logic. The logic is configured to receive repair code associated with a memory instance and assign a compression parameter to the repair code based on a configuration of the memory instance. The logic is also configured to compress the repair code based on the compression parameter to produce compressed repair code and to provide compressed repair data that includes the compressed repair code and compression control data that identifies the compression parameter. A non-volatile memory controller is coupled between the non-volatile memory and the logic. The non-volatile memory controller is configured to transfer the compressed repair data to and/or from the non-volatile memory.
    Type: Grant
    Filed: August 30, 2023
    Date of Patent: March 25, 2025
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Devanathan Varadarajan, Ramakrishnan Venkatasubramanian, Varun Singh
  • Publication number: 20250086576
    Abstract: Techniques for logistics management in a supply chain are described. In one aspect, a first data including a first location and a second location associated with a shipment mix to be transported amongst a plurality of facilities located at different locations is obtained. Further, a second data associated with a product amongst the plurality of products is acquired, where the second data includes a hierarchical information and a historical path information of the product. A derived inventory of the plurality of products available within each facility is computed in correspondence with the second data associated with the product. The derived inventory of each facility is compared with an actual inventory of each facility to generate a reconciled output. The reconciled output is analyzed along with the second data acquired to generate feasible path layouts, from which a recommended path is selected for transporting the shipment mix.
    Type: Application
    Filed: September 13, 2023
    Publication date: March 13, 2025
    Inventors: Varun Singh, Kartikeyan Bollapalli
  • Patent number: 12229403
    Abstract: Aspects of a storage device are provided that handle host commands associated with active and inactive zones using a hybrid L2P mapping system. The storage device includes a NVM, a controller, a first volatile memory and a second volatile memory. The controller allocates, as a superblock, one or more physical blocks respectively in one or more memory dies of the NVM, receives write commands including logical addresses associated with active zones, and stores in an L2P mapping table L2P address mappings of these logical addresses to physical addresses associated with either volatile memory or the superblock. The controller refrains from storing L2P address mappings for inactive zones, instead storing in a superblock mapping table a mapping of superblocks to inactive zones in response to respective zone finish commands. As a result, L2P mapping table sizes are reduced, zone read, reset, and TTR performance are increased, and reduced WAF is achieved.
    Type: Grant
    Filed: September 20, 2022
    Date of Patent: February 18, 2025
    Assignee: SANDISK TECHNOLOGIES, INC.
    Inventors: Chaitanya Kavirayani, Vineet Agarwal, Sampath Raja Murthy, Aakar Deora, Varun Singh
  • Publication number: 20250055901
    Abstract: Disclosed is a method for improving performance of a streaming media session between a plurality of communication entities. Observation reports are collected from a plurality of monitoring entities. Each observation report comprises information pertaining to events observed and recorded at a corresponding monitoring entity. A size of at least one window to be used for analyzing the observation reported is determined. The observation reports are analyzed using the at least one window of the determined size to determine a correlation between the events across the observation reports. A source of a problem encountered during the streaming media session is identified based on the correlation between the events. A notification of the source of the problem is sent to at least one of the monitoring entities.
    Type: Application
    Filed: October 30, 2024
    Publication date: February 13, 2025
    Inventors: Varun Singh, Jörg Ott, Marcin Nagy, Navid Khajehzadeh
  • Patent number: 12217102
    Abstract: An integrated circuit comprises a set of processor cores, wherein each processor core of the set of processor cores includes BIST logic circuitry and multiple memory blocks coupled to the BIST logic circuitry. Each processor core further includes multiple power control circuitry, where each power control circuitry of the multiple power control circuitry is coupled to a respective processor core of the set of processor cores, multiple isolation circuitry, where each isolation circuitry of the multiple isolation circuitry is coupled to a respective processor core of the set of processor cores, a built-in-self repair (BISR) controller coupled to the each of the set of processor cores, each of the multiple power control circuitry, and each of the multiple isolation circuitry, and a safety controller coupled to the BISR controller, the multiple power control circuitry, and to the multiple isolation circuitry.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: February 4, 2025
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Devanathan Varadarajan, Varun Singh, Jose Luis Flores, Rejitha Nair, David Matthew Thompson
  • Publication number: 20250037070
    Abstract: Techniques for identifying aging inventory and generating recommendations for managing the aging inventory are described. In an example, inventory datasets may be retrieved from a centralized repository, such as an EPCIS repository. An inventory dataset includes at least a unique identifier of a product, hierarchy data between different products, and a status of the product at different instances. The inventory datasets may be analysed to identify aging inventory. The aging inventory include a product inventory for which an expiration date is approaching, a product inventory which has stored in an inventory storage facility beyond a stipulated time, and so on. The aging inventory may be identified based on determination of manufacturing date of the products. Based on the aging inventory, recommendations may be generated for disposal of the aging inventory. The recommendations may be based on a set of rules.
    Type: Application
    Filed: July 28, 2023
    Publication date: January 30, 2025
    Inventors: Varun Singh, Santosh Balbhadra Trivedi, Sachin Kulkarni, Kartikeyan Bollapalli, Ankit Parikh
  • Publication number: 20240420057
    Abstract: Systems and methods for collecting and displaying business insights in a cloud-based system. Steps include obtaining data from a cloud-based system associated with any of applications, infrastructure, and employees of an organization, wherein the cloud-based system includes a plurality of organizations with the applications, infrastructure, and employees each assigned thereto; processing the data associated with the organization to determine a plurality of insights; and displaying the plurality of insights on a per-organization basis based on the processing.
    Type: Application
    Filed: June 11, 2024
    Publication date: December 19, 2024
    Applicant: Zscaler, Inc.
    Inventors: Umamaheswaran Arumugam, Varun Singh, Jun Xue, Chakkaravarthy Periyasamy Balaiah, Jasbir Kaushal, Abhishek Bathla, Shankar Vivekanandan, Santhosh Kumar, Anoma Dhurka, Raj Krishna, Valentin Khechinashvili, Pranab Sharma
  • Patent number: 12160460
    Abstract: Disclosed is a method for improving performance of a streaming media session between a plurality of communicating entities. Observation reports are collected from a plurality of monitoring entities. Each observation report comprises information pertaining to events observed and recorded at a corresponding monitoring entity. A size of at least one window to be used for analyzing the observation reports is determined. The observation reports are analyzed using the at least one window of the determined size, to determine a correlation between the events across the observation reports. A problem encountered during the streaming media session is identified, based upon the correlation between the events. A notification is sent to at least one of the monitoring entities, based upon the problem. The notification is sent during the streaming media session.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: December 3, 2024
    Inventors: Varun Singh, Jörg Ott, Marcin Nagy, Navid Khajehzadeh
  • Patent number: 12137108
    Abstract: Systems and methods for visualization monitoring data from a cloud-based system include obtaining the monitoring data, wherein the monitoring data is based on transactions associated with a plurality of users of the cloud-based system; providing a Graphical User Interface (GUI); obtaining a plurality of filter selections for a plurality of filter types; and displaying a visualization comprising a Sankey diagram of the monitoring data with nodes in the Sankey diagram including each of the plurality of filter types and links between the nodes indicative of the transactions in the monitoring data. The monitoring data can be for one or more of cloud security service transactions, application access via a Zero Trust Network Access (ZTNA) service, and user experience metrics.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: November 5, 2024
    Assignee: Zscaler, Inc.
    Inventors: Amit Sinha, Jasbir Singh Kaushal, Tiffany Bui, Sundar Rajkumar Jothimani, Priyanka Pani, Varun Singh
  • Publication number: 20240321378
    Abstract: Circuits and methods are directed to repairable memory systems and memory repair processes. An example circuit includes first and second logic coupled together. The first logic receives a plurality of instances of defect data from a plurality of memories, respectively, in which each of the plurality of instances of defect data has a memory-specific format. The first logic converts each of the plurality of instances of defect data to a common format and merges the plurality instances of defect data in the common format to generate merged data. The second logic receives the merged data and determines a plurality of instances of repair data for the plurality of instances of defect data, respectively, based on the merged data.
    Type: Application
    Filed: June 7, 2024
    Publication date: September 26, 2024
    Inventors: Devanathan VARADARAJAN, Varun SINGH
  • Patent number: 12072731
    Abstract: An electronic device comprising one or more subcircuits configured to receive a clock signal, the clock signal configured to switch from a reference clock signal to a second clock signal based on a clock bypass signal, a timer configured to receive the reference clock signal and output an alignment signal based on the reference clock signal, wherein a frequency of the alignment signal is determined based on clock frequencies of the one or more subcircuits; a clock alignment module coupled to the timer and the one or more subcircuits and configured to receive the clock bypass signal, determine that the clock bypass signal has changed to switch the one or more subcircuits to the reference clock signal from the second clock signal, block the clock signal from being received by the one or more subcircuits, receive the alignment signal, and unblock the clock signal based on the alignment signal.
    Type: Grant
    Filed: May 15, 2023
    Date of Patent: August 27, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Varun Singh, Rejitha Nair, John Chrysostom Apostol, Venkateswar Reddy Kowkutla, Santhanagopal Raghavendra
  • Patent number: 12039280
    Abstract: Machine classifiers in accordance with embodiments of the invention capture long-term temporal dependencies in particular tasks, such as turn-based dialogues. Machine classifiers may be used to help users to perform tasks indicated by the user. When a user utterance is received, natural language processing techniques may be used to understand the user's intent. Templates may be determined based on the user's intent in the generation of responses to solicit information from the user. A variety of persona attributes may be determined for a user. The persona attributes may be determined based on the user's utterances and/or provided as metadata included with the user's utterances. A response persona may be used to generate responses to the user's utterances such that the generated responses match a tone appropriate to the task. A response persona may be used to generate templates to solicit additional information and/or generate responses appropriate to the task.
    Type: Grant
    Filed: April 17, 2023
    Date of Patent: July 16, 2024
    Assignee: Capital One Services, LLC
    Inventors: Oluwatobi Olabiyi, Erik T. Mueller, Rui Zhang, Zachary Kulis, Varun Singh
  • Patent number: 12032910
    Abstract: Systems described herein may use transformer-based machine classifiers to perform a variety of natural language understanding tasks including, but not limited to sentence classification, named entity recognition, sentence similarity, and question answering. The exceptional performance of transformer-based language models is due to their ability to capture long-term temporal dependencies in input sequences. Machine classifiers may be trained using training data sets for multiple tasks, such as but not limited to sentence classification tasks and sequence labeling tasks. Loss masking may be employed in the machine classifier to jointly train the machine classifier on multiple tasks simultaneously. The user of transformer encoders in the machine classifiers, which treat each output sequence independently of other output sequences, in accordance with aspects of the invention do not require joint labeling to model tasks.
    Type: Grant
    Filed: September 26, 2022
    Date of Patent: July 9, 2024
    Assignee: Capital One Services, LLC
    Inventors: Oluwatobi Olabiyi, Erik T. Mueller, Zachary Kulis, Varun Singh
  • Patent number: 12033711
    Abstract: In a described example, an integrated circuit (IC) includes a repairable memory system. A repair controller is coupled to the repairable memory system. The repair controller includes compression logic configured to encode memory repair code data for a respective instance of the repairable memory system and provide compressed repair data. A non-volatile memory controller is coupled to the repair controller and to non-volatile memory. The non-volatile memory controller is configured to transfer the compressed repair data to the non-volatile memory for storage.
    Type: Grant
    Filed: April 17, 2023
    Date of Patent: July 9, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Devanathan Varadarajan, Varun Singh
  • Patent number: 12009045
    Abstract: A system includes a processor and a memory set coupled to the processor. The system also includes a repair circuit coupled to the memory set. The repair circuit includes a first repair circuit and a second repair circuit. The repair circuit also includes a test controller configured to select between the first repair circuit and the second repair circuit to perform an in-field self-repair of the memory set.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: June 11, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Devanathan Varadarajan, Varun Singh
  • Publication number: 20240163312
    Abstract: Systems and methods are provided for calculating a security risk score. In one implementation, a method includes the step of analyzing a network to assess a license status of the network, where the license status is related to one or more security licenses procured for providing security protection to the network. The method also includes the step of analyzing the network to assess a configuration status of the network, where the configuration status is related to configurations settings of one or more security policies currently operating with respect to the network. Based on the assessed license status and configuration status, the method further includes the step of calculating a security risk score indicating a current level of risk that the network faces against threats, intrusions, cyber-attacks, breaches, and/or data loss.
    Type: Application
    Filed: June 9, 2023
    Publication date: May 16, 2024
    Inventors: Rubin Azad, Deepen Desai, Varun Singh, Shriyash Shete
  • Publication number: 20240094903
    Abstract: Aspects of a storage device are provided that handle host commands associated with active and inactive zones using a hybrid L2P mapping system. The storage device includes a NVM, a controller, a first volatile memory and a second volatile memory. The controller allocates, as a superblock, one or more physical blocks respectively in one or more memory dies of the NVM, receives write commands including logical addresses associated with active zones, and stores in an L2P mapping table L2P address mappings of these logical addresses to physical addresses associated with either volatile memory or the superblock. The controller refrains from storing L2P address mappings for inactive zones, instead storing in a superblock mapping table a mapping of superblocks to inactive zones in response to respective zone finish commands. As a result, L2P mapping table sizes are reduced, zone read, reset, and TTR performance are increased, and reduced WAF is achieved.
    Type: Application
    Filed: September 20, 2022
    Publication date: March 21, 2024
    Inventors: Chaitanya KAVIRAYANI, Vineet AGARWAL, Sampath RAJA MURTHY, Aakar DEORA, Varun SINGH
  • Publication number: 20230409435
    Abstract: One example includes an integrated circuit (IC). The IC includes non-volatile memory and logic. The logic is configured to receive repair code associated with a memory instance and assign a compression parameter to the repair code based on a configuration of the memory instance. The logic is also configured to compress the repair code based on the compression parameter to produce compressed repair code and to provide compressed repair data that includes the compressed repair code and compression control data that identifies the compression parameter. A non-volatile memory controller is coupled between the non-volatile memory and the logic. The non-volatile memory controller is configured to transfer the compressed repair data to and/or from the non-volatile memory.
    Type: Application
    Filed: August 30, 2023
    Publication date: December 21, 2023
    Inventors: Devanathan Varadarajan, Ramakrishnan Venkatasubramanian, Varun Singh
  • Patent number: 11836135
    Abstract: Roughly described, a database accelerator is installed in a network having client systems which makes database queries to a particular IP address and port, and database servers which accept queries received at an IP address and port. The accelerator includes a cache, and is arranged to receive, through a network port, a database query made by a client system and directed to the particular IP address and port, return response data from the cache if available there, and if not, then forward the query through a network port to the database servers. Upon receipt of response data from the servers, the accelerator can retain it in its cache in addition to forwarding it back to the client. By installing the accelerator transparently in the network, no changes are required to either the client or server software in order to add query caching functionality to an existing client/server database arrangement.
    Type: Grant
    Filed: June 9, 2021
    Date of Patent: December 5, 2023
    Assignee: Ignite ScalArc Solutions, Inc.
    Inventors: Varun Singh, Uday V. Sawant, Prateek Goel, Naresh G. Deshaveni