Abstract: A system for performing hashing includes a controller for controlling the system and for providing a clock signal; an array of integrated circuits; in each integrated circuit, a plurality of cores for performing hashing; and in each core, a plurality of data expanders and data compressors, the data expanders and the data compressors having pipelined circuitry so that two iterations of a hashing loop are performed for each cycle of the clock signal. A method for performing hashing, includes controlling a system having an array of integrated circuits with a clock signal; performing hashing in a plurality of cores in each integrated circuit; and performing for each cycle of the clock signal, in each core, a plurality of data expansion and data compression operations, using pipelined circuitry so that two iterations of a hashing loop are performed for each cycle of the clock signal.

Abstract: A system for performing hashing includes a controller for controlling the system and for providing a clock signal; an array of integrated circuits; in each integrated circuit, a plurality of cores for performing hashing; and in each core, a plurality of data expanders and data compressors, the data expanders and the data compressors having pipelined circuitry so that two iterations of a hashing loop are performed for each cycle of the clock signal. A method for performing hashing, includes controlling a system having an array of integrated circuits with a clock signal; performing hashing in a plurality of cores in each integrated circuit; and performing for each cycle of the clock signal, in each core, a plurality of data expansion and data compression operations, using pipelined circuitry so that two iterations of a hashing loop are performed for each cycle of the clock signal.

Abstract: An asynchronous debug interface is disclosed that allows TAG agents, JTAG-based debuggers, firmware, and software to debug, access, and override any functional registers, interrupt registers, power/clock gating enables, etc., of core logic being tested. The asynchronous debug interface works at a wide range of clock frequencies and allows read and write transactions to take place on a side channel, as well as within the on chip processor fabric without switching into a debug or test mode. The asynchronous debug interface works with two-wire and four-wire JTAG controller configurations, and is compliant with IEEE standards, such as 1149.1, 1149.7, etc., and provides an efficient and seamless way to debug complex system-on-chip states and system-on-chip products.

Abstract: An asynchronous debug interface is disclosed that allows TAG agents, JTAG-based debuggers, firmware, and software to debug, access, and override any functional registers, interrupt registers, power/clock gating enables, etc., of core logic being tested. The asynchronous debug interface works at a wide range of clock frequencies and allows read and write transactions to take place on a side channel, as well as within the on chip processor fabric without switching into a debug or test mode. The asynchronous debug interface works with two-wire and four-wire JTAG controller configurations, and is compliant with IEEE standards, such as 1149.1, 1149.7, etc., and provides an efficient and seamless way to debug complex system-on-chip states and system-on-chip products.

Abstract: A method and apparatus for transferring data traffic, such as in a SONET/SDH environment, is provided. Two designs are presented, each utilizing a dual device design, where one device performs GFP Framing and the other device performs GFP-T adaptation. The method and apparatus include a first device having a first device FIFO, the first device configured to receive data and assemble data into packets and transfer data across a packet interface when the first device FIFO contains more than N bytes. A second device comprises a second device FIFO, the second device configured to receive data packets from the packet interface and utilize a plurality of thresholds to maintain a quantity of data in the second device FIFO within a predetermined range. Depending on the design employed, control codes, such as 65B_PAD control codes, may be added in the first device under certain conditions to facilitate data transfer.

Abstract: A device for mapping and demapping cells in an orderly manner is provided. The device employs a channel identifier and in certain configurations a buffer and series of stages to provide for relatively ordered, predictable mapping and demapping of data, such as virtual concatenation data.

Abstract: A shared buffer for near-end and optical interface flow control in fiber optic communications is described. In one embodiment, the invention includes receiving data from a client as frames in a first format, storing the data in a addressable buffer, recording addresses for the end of each received frame, reading the stored data from the buffer for conversion to frames of a second format, and sending a ready signal to the client upon reading data stored at a recorded address for the end of a received frame.