Patents by Inventor Vasant B. Rao
Vasant B. Rao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10360329Abstract: Embodiments relate to multi-cycle signal identification for static timing analysis. An aspect includes identifying, in a circuit under test, a multi-cycle signal, the multi-cycle signal having a longer period than a main clock signal of the circuit under test. Another aspect includes mapping a plurality of additional signals of the circuit under test onto the multi-cycle signal, the plurality of additional signals each having a shorter period than the multi-cycle signal. Yet another aspect includes performing static timing analysis of the circuit under test based on the multi-cycle signal.Type: GrantFiled: January 25, 2017Date of Patent: July 23, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert J. Allen, Vasant B. Rao, William J. Wright, Xin Zhao
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Patent number: 10325059Abstract: A method, system, and computer program product for performing incremental common path pessimism analysis in integrated circuit design includes performing common path pessimism removal (CPPR) analysis to provide timing credit for one or more paths that are subject to common path pessimism. The method also includes identifying one or more post-CPPR critical paths based on the CPPR analysis, setting flags for critical nodes of the one or more post-CPPR critical paths, performing a design fix to address the one or more post-CPPR critical paths, and applying a set of rules based on the design fix and the flags to identify seed points among the critical nodes of the one or more post-CPPR critical paths. Invalidating and re-performing the CPPR analysis is done only for paths associated with the seed points.Type: GrantFiled: October 27, 2017Date of Patent: June 18, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Tsung-Wei Huang, Kerim Kalafala, Vasant B. Rao, Debjit Sinha, Natesan Venkateswaran
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Publication number: 20190138916Abstract: Aspects include creating a knowledge base that identifies experts in a set of domains. Front-end processing is provided to an issue tracking system. The front-end processing includes receiving a report of an issue related to one of the domains, and accessing the knowledge base to locate an expert in the domain. The front-end processing also includes instructing the issue tracking system to route the received report of the issue to the located expert in the domain. The issue tracking system executes on a different processor than the front-end processing. Data collected from operation of the issue tracking system is monitored, and the knowledge base is updated based at least in part on the data collected from the operation of the issue tracking system.Type: ApplicationFiled: November 9, 2017Publication date: May 9, 2019Inventors: Robert J. Allen, Adil Bhanji, Vasant B. Rao, Peter A. Twombly, Loma D. Vaishnav, Xin Zhao
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Publication number: 20180046748Abstract: A method, system, and computer program product for performing incremental common path pessimism analysis in integrated circuit design includes performing common path pessimism removal (CPPR) analysis to provide timing credit for one or more paths that are subject to common path pessimism. The method also includes identifying one or more post-CPPR critical paths based on the CPPR analysis, setting flags for critical nodes of the one or more post-CPPR critical paths, performing a design fix to address the one or more post-CPPR critical paths, and applying a set of rules based on the design fix and the flags to identify seed points among the critical nodes of the one or more post-CPPR critical paths. Invalidating and re-performing the CPPR analysis is done only for paths associated with the seed points.Type: ApplicationFiled: October 27, 2017Publication date: February 15, 2018Inventors: Tsung-Wei Huang, Kerim Kalafala, Vasant B. Rao, Debjit Sinha, Natesan Venkateswaran
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Patent number: 9836572Abstract: A method, system, and computer program product for performing incremental common path pessimism analysis in integrated circuit design includes performing common path pessimism removal (CPPR) analysis to provide timing credit for one or more paths that are subject to common path pessimism. The method also includes identifying one or more post-CPPR critical paths based on the CPPR analysis, setting flags for critical nodes of the one or more post-CPPR critical paths, performing a design fix to address the one or more post-CPPR critical paths, and applying a set of rules based on the design fix and the flags to identify seed points among the critical nodes of the one or more post-CPPR critical paths. Invalidating and re-performing the CPPR analysis is done only for paths associated with the seed points.Type: GrantFiled: November 19, 2015Date of Patent: December 5, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Tsung-Wei Huang, Kerim Kalafala, Vasant B. Rao, Debjit Sinha, Natesan Venkateswaran
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Patent number: 9785737Abstract: A method, system, and computer program product to perform parallel multi-threaded common path pessimism removal in integrated circuit design include constructing, using a processor, a thread-specific graphical representation (TSGR) relating to each data node and clock node pair and performing processes in parallel for each TSGR. The processes include determining initial arrival times at the data node and the clock node, computing initial test slack based on the initial arrival times at the data node and the clock node, identifying fan-out nodes among the additional nodes, each fan-out node being an origin of at least two of the edges in the two or more paths to the clock node, generating one or more tags based the fan-out nodes, determining adjusted arrival times based on the one or more tags, and computing adjusted test slack based on the adjusted arrival times.Type: GrantFiled: November 17, 2015Date of Patent: October 10, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David J. Hathaway, Kerim Kalafala, Vasant B. Rao, Alexander J. Suess, Vladimir Zolotov
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Patent number: 9760665Abstract: An approach is provided in which an information handling system executes multiple timing constraint sensitivity tests on a circuit model using a first signal arrival time and generates multiple test results. The information handling system compares the multiple test results with a pre-determined probability threshold and, in response to determining that an amount of test failures included in the multiple test results meets a pre-determined failure probability threshold, the information handling system computes a timing constraint sensitivity of the circuit model based upon the first signal arrival time.Type: GrantFiled: August 22, 2015Date of Patent: September 12, 2017Assignee: International Business Machines CorporationInventors: Sachin K. Gupta, Vasant B. Rao, Suriya T. Skariah, James E. Sundquist, James D. Warnock
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Patent number: 9760664Abstract: An approach is provided in which an information handling system executes multiple timing constraint sensitivity tests on a circuit model using a first signal arrival time and generates multiple test results. The information handling system compares the multiple test results with a pre-determined probability threshold and, in response to determining that an amount of test failures included in the multiple test results meets a pre-determined failure probability threshold, the information handling system computes a timing constraint sensitivity of the circuit model based upon the first signal arrival time.Type: GrantFiled: July 7, 2015Date of Patent: September 12, 2017Assignee: International Business Machines CorporationInventors: Sachin K. Gupta, Vasant B. Rao, Suriya T. Skariah, James E. Sundquist, James D. Warnock
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Publication number: 20170206294Abstract: Embodiments relate to multi-cycle signal identification for static timing analysis. An aspect includes identifying, in a circuit under test, a multi-cycle signal, the multi-cycle signal having a longer period than a main clock signal of the circuit under test. Another aspect includes mapping a plurality of additional signals of the circuit under test onto the multi-cycle signal, the plurality of additional signals each having a shorter period than the multi-cycle signal. Yet another aspect includes performing static timing analysis of the circuit under test based on the multi-cycle signal.Type: ApplicationFiled: January 25, 2017Publication date: July 20, 2017Inventors: Robert J. Allen, Vasant B. Rao, William J. Wright, Xin Zhao
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Publication number: 20170147737Abstract: A method, system, and computer program product for performing incremental common path pessimism analysis in integrated circuit design includes performing common path pessimism removal (CPPR) analysis to provide timing credit for one or more paths that are subject to common path pessimism. The method also includes identifying one or more post-CPPR critical paths based on the CPPR analysis, setting flags for critical nodes of the one or more post-CPPR critical paths, performing a design fix to address the one or more post-CPPR critical paths, and applying a set of rules based on the design fix and the flags to identify seed points among the critical nodes of the one or more post-CPPR critical paths. Invalidating and re-performing the CPPR analysis is done only for paths associated with the seed points.Type: ApplicationFiled: November 19, 2015Publication date: May 25, 2017Inventors: Tsung-Wei Huang, Kerim Kalafala, Vasant B. Rao, Debjit Sinha, Natesan Venkateswaran
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Publication number: 20170140089Abstract: A method, system, and computer program product to perform parallel multi-threaded common path pessimism removal in integrated circuit design include constructing, using a processor, a thread-specific graphical representation (TSGR) relating to each data node and clock node pair and performing processes in parallel for each TSGR. The processes include determining initial arrival times at the data node and the clock node, computing initial test slack based on the initial arrival times at the data node and the clock node, identifying fan-out nodes among the additional nodes, each fan-out node being an origin of at least two of the edges in the two or more paths to the clock node, generating one or more tags based the fan-out nodes, determining adjusted arrival times based on the one or more tags, and computing adjusted test slack based on the adjusted arrival times.Type: ApplicationFiled: November 17, 2015Publication date: May 18, 2017Inventors: David J. Hathaway, Kerim Kalafala, Vasant B. Rao, Alexander J. Suess, Vladimir Zolotov
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Patent number: 9613171Abstract: Embodiments relate to multi-cycle signal identification for static timing analysis. An aspect includes identifying, in a circuit under test, a multi-cycle signal, the multi-cycle signal having a longer period than a main clock signal of the circuit under test. Another aspect includes mapping a plurality of additional signals of the circuit under test onto the multi-cycle signal, the plurality of additional signals each having a shorter period than the multi-cycle signal. Yet another aspect includes performing static timing analysis of the circuit under test based on the multi-cycle signal.Type: GrantFiled: January 15, 2016Date of Patent: April 4, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert J. Allen, Vasant B. Rao, William J. Wright, Xin Zhao
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Publication number: 20170011154Abstract: An approach is provided in which an information handling system executes multiple timing constraint sensitivity tests on a circuit model using a first signal arrival time and generates multiple test results. The information handling system compares the multiple test results with a pre-determined probability threshold and, in response to determining that an amount of test failures included in the multiple test results meets a pre-determined failure probability threshold, the information handling system computes a timing constraint sensitivity of the circuit model based upon the first signal arrival time.Type: ApplicationFiled: July 7, 2015Publication date: January 12, 2017Inventors: SACHIN K. GUPTA, VASANT B. RAO, SURIYA T. SKARIAH, JAMES E. SUNDQUIST, JAMES D. WARNOCK
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Publication number: 20170011153Abstract: An approach is provided in which an information handling system executes multiple timing constraint sensitivity tests on a circuit model using a first signal arrival time and generates multiple test results. The information handling system compares the multiple test results with a pre-determined probability threshold and, in response to determining that an amount of test failures included in the multiple test results meets a pre-determined failure probability threshold, the information handling system computes a timing constraint sensitivity of the circuit model based upon the first signal arrival time.Type: ApplicationFiled: August 22, 2015Publication date: January 12, 2017Inventors: SACHIN K. GUPTA, VASANT B. RAO, SURIYA T. SKARIAH, JAMES E. SUNDQUIST, JAMES D. WARNOCK
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Publication number: 20160364519Abstract: Examples of techniques for analyzing and generating timing reports for circuits are described herein. A computer-implemented method includes splitting a netlist or cross section of a circuit into sub-circuits. The method further includes building a timing graph by combining generated timing models of the sub-circuits. The method includes determining a full set of dependencies based on each sub-circuit's dependent configuration parameters. The method also further includes generating a sample plan for each sub-circuit. The method includes receiving results from a simulation for each sub-circuit based on the sample plan for each sub-circuit. The method includes generating algebraic forms for an early delay, a late delay, and a slew by curve fitting across the configuration parameters. The method includes propagating arrival times and slew in algebraic forms throughout the timing graph. The method includes evaluating checks based on selected projections from the timing graph to find a worst slack configuration.Type: ApplicationFiled: June 11, 2015Publication date: December 15, 2016Inventors: Robert J. Allen, Yanai Danan, Vasant B. Rao, Xin Zhao
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Patent number: 9501608Abstract: Examples of techniques for analyzing and generating timing reports for circuits are described herein. A computer-implemented method includes splitting a netlist or cross section of a circuit into sub-circuits. The method further includes building a timing graph by combining generated timing models of the sub-circuits. The method includes determining a full set of dependencies based on each sub-circuit's dependent configuration parameters. The method also further includes generating a sample plan for each sub-circuit. The method includes receiving results from a simulation for each sub-circuit based on the sample plan for each sub-circuit. The method includes generating algebraic forms for an early delay, a late delay, and a slew by curve fitting across the configuration parameters. The method includes propagating arrival times and slew in algebraic forms throughout the timing graph. The method includes evaluating checks based on selected projections from the timing graph to find a worst slack configuration.Type: GrantFiled: June 11, 2015Date of Patent: November 22, 2016Assignee: International Business Machines CorporationInventors: Robert J. Allen, Yanai Danan, Vasant B. Rao, Xin Zhao
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Patent number: 7643981Abstract: The present invention provides for simulating signal transitions. Circuit characteristics are generated. Circuit characteristics are loaded into memory. Circuit behaviour is simulated. A non-leading edge circuit transition is captured. This occurs in software.Type: GrantFiled: July 22, 2004Date of Patent: January 5, 2010Assignee: International Business Machines CorporationInventors: Sang Y. Lee, Vasant B. Rao, Jeffrey Soreff, James Warnock, David Winston
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Patent number: 6763504Abstract: A method for further reducing RC parasitics in an interconnect network following internal node elimination is described. A resistor is initially selected as a candidate for shorting, and it is established whether the accumulated delay error at either end of the resistor is less than a predetermined threshold. This threshold must be a fraction of the time-constant threshold selected by internal node elimination techniques in order to limit the growth of the accumulated delay errors. An important aspect of the invention is the simplicity of the formula used to change the downstream resistor values, namely, the product of the value of the resistor shorted and the ratio of the cumulative downstream capacitances of the two ends of the resistor whose value is being changed. This particular choice of updating the downstream resistor values minimizes the absolute-value of the delay errors at every node due to shorting of the selected resistor.Type: GrantFiled: September 6, 2002Date of Patent: July 13, 2004Assignee: International Business Machines CorporationInventors: Vasant B. Rao, Ravichander Ledalla, Jeffrey P. Soreff, Fred L. Yang
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Publication number: 20040049746Abstract: A method for further reducing RC parasitics in an interconnect network following internal node elimination is described. A resistor is initially selected as a candidate for shorting, and it is established whether the accumulated delay error at either end of the resistor is less than a predetermined threshold. This threshold must be a fraction of the time-constant threshold selected by internal node elimination techniques in order to limit the growth of the accumulated delay errors. An important aspect of the invention is the simplicity of the formula used to change the downstream resistor values, namely, the product of the value of the resistor shorted and the ratio of the cumulative downstream capacitances of the two ends of the resistor whose value is being changed. This particular choice of updating the downstream resistor values minimizes the absolute-value of the delay errors at every node due to shorting of the selected resistor.Type: ApplicationFiled: September 6, 2002Publication date: March 11, 2004Applicant: International Business Machine CorporationInventors: Vasant B. Rao, Ravichander Ledalla, Jeffrey P. Soreff, Fred L. Yang
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Publication number: 20030182639Abstract: A transistor-level simulator system and method which uses a simulator=s API=s construct a circuit code module which is used to perform circuit simulation of input and output wave forms without the user having to provide a detailed netlist. This circuit simulation tool may be used on more complex gates where other models may be impractical to obtain without loss in the fidelity of the waveforms.Type: ApplicationFiled: March 25, 2002Publication date: September 25, 2003Applicant: International Business Machines CorporationInventors: Timothy S. Lehner, Vasant B. Rao