Patents by Inventor Vasant Palisetti

Vasant Palisetti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for addressing and improving holds in logic networks
    Patent number: 8347250
    Abstract: A method and apparatus for modifying a synchronous logic network so that the hold slack calculated at all pins is greater than or equal to a user-specified threshold, with the condition that the setup slack at any pin does not become negative or smaller than a user-specified margin. The result is an improved design which is less likely to fail due to a hold time violation. The method and apparatus introduce a limited number of logic cells which helps keep power consumption and design size to a minimum.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: January 1, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: George A. Gonzalez, Pete J. Hannan, William A. McGee, Vasant Palisetti, Ashok Venkatachar
  • Identification of critical enables using MEA and WAA metrics
    Patent number: 8266569
    Abstract: A plurality of sequential nodes in a design file for an electronic device are identified and one or more combinatorial power metric values are computed for the plurality of sequential nodes based upon an effective switching capacitance, a switching activity measure, and a power effort measure for at least a first device downstream from the each sequential node at a specified depth. The combinatorial power metric values for the plurality of sequential node are stored and compared to a target power metric value to determine if power consumption at the electronic device meets a predetermined power performance goal.
    Type: Grant
    Filed: March 5, 2010
    Date of Patent: September 11, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Vasant Palisetti, Rachida Kebichi, Samuel Naffziger
  • METHOD AND APPARATUS FOR ADDRESSING AND IMPROVING HOLDS IN LOGIC NETWORKS
    Publication number: 20120167030
    Abstract: A method and apparatus for modifying a synchronous logic network so that the hold slack calculated at all pins is greater than or equal to a user-specified threshold, with the condition that the setup slack at any pin does not become negative or smaller than a user-specified margin. The result is an improved design which is less likely to fail due to a hold time violation. The method and apparatus introduce a limited number of logic cells which helps keep power consumption and design size to a minimum.
    Type: Application
    Filed: December 22, 2010
    Publication date: June 28, 2012
    Applicant: Advanced Micro Devices, Inc.
    Inventors: George A. Gonzalez, Pete J. Hannan, William A. McGee, Vasant Palisetti, Ashok Venkatachar
  • Identification of Critical Enables Using MEA and WAA Metrics
    Publication number: 20110218779
    Abstract: A plurality of sequential nodes in a design file for an electronic device are identified and one or more combinatorial power metric values are computed for the plurality of sequential nodes based upon an effective switching capacitance, a switching activity measure, and a power effort measure for at least a first device downstream from the each sequential node at a specified depth. The combinatorial power metric values for the plurality of sequential node are stored and compared to a target power metric value to determine if power consumption at the electronic device meets a predetermined power performance goal.
    Type: Application
    Filed: March 5, 2010
    Publication date: September 8, 2011
    Inventors: Vasant Palisetti, Rachida Kebichi, Samuel Naffziger
  • Method of designing an electronic device and device thereof
    Patent number: 7870521
    Abstract: A plurality of sequential nodes in a design file for an electronic device are identified and an effective switching capacitance is determined for a first sequential node of the plurality of sequential nodes based upon statically predicted operation of a first device downstream from the first sequential node. The effective switching capacitance for the first sequential node is stored, and the process is repeated for the other identified sequential nodes in the design file.
    Type: Grant
    Filed: February 27, 2008
    Date of Patent: January 11, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Vasant Palisetti
  • METHOD OF DESIGNING AN ELECTRONIC DEVICE AND DEVICE THEREOF
    Publication number: 20090217220
    Abstract: A plurality of sequential nodes in a design file for an electronic device are identified and an effective switching capacitance is determined for a first sequential node of the plurality of sequential nodes based upon statically predicted operation of a first device downstream from the first sequential node. The effective switching capacitance for the first sequential node is stored, and the process is repeated for the other identified sequential nodes in the design file.
    Type: Application
    Filed: February 27, 2008
    Publication date: August 27, 2009
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventor: Vasant Palisetti