Patents by Inventor Vasant Rao
Vasant Rao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240037005Abstract: An example method for monitoring operations of a business organization electronic computing device includes executing a checklist on a monitoring electronic computing device to obtain an operational status of an application being implemented on the business organization electronic computing device. Data is received from the business organization electronic computing device regarding the operational status of the application being implemented on the business organization electronic computing device. When a determination is made that the data identifies an operational threat for the business organization electronic computing device, an action is proposed or implemented to remediate the operational threat. An implementation of the checklist is adjusted based on an effectiveness of the action to remediate the operational threat.Type: ApplicationFiled: October 6, 2023Publication date: February 1, 2024Inventors: Parul Ghosh, Shishir Vasant Rao, Niravkumar N. Bajaj, Priyanka Dixit, Arvind Kumar Gottapally, Abhishek Kumar
-
Patent number: 11829274Abstract: An example method for monitoring operations of a business organization electronic computing device includes executing a checklist on a monitoring electronic computing device to obtain an operational status of an application being implemented on the business organization electronic computing device. Data is received from the business organization electronic computing device regarding the operational status of the application being implemented on the business organization electronic computing device. When a determination is made that the data identifies an operational threat for the business organization electronic computing device, an action is proposed or implemented to remediate the operational threat. An implementation of the checklist is adjusted based on an effectiveness of the action to remediate the operational threat.Type: GrantFiled: January 13, 2020Date of Patent: November 28, 2023Assignee: Wells Fargo Bank, N.A.Inventors: Parul Ghosh, Shishir Vasant Rao, Niravkumar N. Bajaj, Priyanka Dixit, Arvind Kumar Gottapally, Abhishek Kumar
-
Patent number: 11263572Abstract: An example method for rendering a dynamic dashboard for an electronic computing device includes receiving data regarding a server computing device. The data indicates whether there are any current or potential problems that impact an operation of the server computing device. Information is obtained regarding any business applications currently running on the server computing device. Information is obtained regarding customers using the business applications currently running on the server computing device. The dynamic dashboard is created to include the information regarding the customers and the business applications currently running on the server computing device and that describes any current or potential problems based on the data. Content of the dynamic dashboard is tailored based upon an identity of an individual who is accessing the dynamic dashboard. The dynamic dashboard is rendered on the electronic computing device.Type: GrantFiled: December 10, 2020Date of Patent: March 1, 2022Assignee: Wells Fargo Bank, N.A.Inventors: Parul Ghosh, Shishir Vasant Rao, Niravkumar N. Bajaj, Priyanka Dixit, Arvind Kumar Gottapally, Abhishek Kumar
-
Patent number: 11093675Abstract: A statistical single-input switching (SIS) timing value is obtained for a first input of a device. A side input with an arc to a common output of a circuit is selected and a statistical skew for the first input and the selected side input of the circuit is obtained. An expected-value for a statistical scale factor distribution is convolved and computed based on the statistical skew. The statistical single-input switching (SIS) timing value is scaled with a final effective statistical scale factor based on the expected-value; optionally, sensitivities of the statistical timing value to variational parameters are chain-ruled with the sensitivities of the statistical skew to variational parameters; and a statistical timing analysis of a given VLSI design is generated based on the scaled (and optionally, chain-ruled) statistical single-input switching (SIS) timing value to create the improved VLSI circuit design.Type: GrantFiled: March 18, 2020Date of Patent: August 17, 2021Assignee: International Business Machines CorporationInventors: Debjit Sinha, Vasant Rao, Michael Hemsley Wood
-
Patent number: 10949593Abstract: A method of performing transistor simulation with improved sensitivity to parasitic by model order reduction in transistor-level timing is disclosed. The method includes reducing a number of derivative calculations during transistor simulation by representing parasitics as a reduced-order model, wherein the reducing includes: compressing the parasitics to a reduced-order model; simulating with load which is replaced with the reduced-order model; differentiating results of the simulation with respect to reduced-order model parameters; differentiating parameters of the reduced-order model with respect to parasitic values; differentiating the parasitic values with respect to statistical parameters; and computing the differential results of the simulation with respect to the statistical parameters via chain ruling.Type: GrantFiled: July 12, 2019Date of Patent: March 16, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert J. Allen, Yanai Danan, Vasant Rao, Jeffrey P. Soreff, Xin Zhao
-
Patent number: 10936982Abstract: An example method for rendering a dynamic dashboard for an electronic computing device includes receiving data regarding a server computing device. The data indicates whether there are any current or potential problems that impact an operation of the server computing device. Information is obtained regarding any business applications currently running on the server computing device. Information is obtained regarding customers using the business applications currently running on the server computing device. The dynamic dashboard is created to include the information regarding the customers and the business applications currently running on the server computing device and that describes any current or potential problems based on the data. Content of the dynamic dashboard is tailored based upon an identity of an individual who is accessing the dynamic dashboard. The dynamic dashboard is rendered on the electronic computing device.Type: GrantFiled: January 13, 2020Date of Patent: March 2, 2021Assignee: Wells Fargo Bank, N.A.Inventors: Parul Ghosh, Shishir Vasant Rao, Niravkumar N. Bajaj, Priyanka Dixit, Arvind Kumar Gottapally, Abhishek Kumar
-
Publication number: 20190332735Abstract: A method of performing transistor simulation with improved sensitivity to parasitic by model order reduction in transistor-level timing is disclosed. The method includes reducing a number of derivative calculations during transistor simulation by representing parasitics as a reduced-order model, wherein the reducing includes: compressing the parasitics to a reduced-order model; simulating with load which is replaced with the reduced-order model; differentiating results of the simulation with respect to reduced-order model parameters; differentiating parameters of the reduced-order model with respect to parasitic values; differentiating the parasitic values with respect to statistical parameters; and computing the differential results of the simulation with respect to the statistical parameters via chain ruling.Type: ApplicationFiled: July 12, 2019Publication date: October 31, 2019Inventors: Robert J. ALLEN, Yanai DANAN, Vasant RAO, Jeffrey P. SOREFF, Xin ZHAO
-
Patent number: 10394986Abstract: A method of performing transistor simulation with improved sensitivity to parasitic by model order reduction in transistor-level timing is disclosed. The method includes reducing a number of derivative calculations during transistor simulation by representing parasitics as a reduced-order model, wherein the reducing includes: compressing the parasitics to a reduced-order model; simulating with load which is replaced with the reduced-order model; differentiating results of the simulation with respect to reduced-order model parameters; differentiating parameters of the reduced-order model with respect to parasitic values; differentiating the parasitic values with respect to statistical parameters; and computing the differential results of the simulation with respect to the statistical parameters via chain ruling.Type: GrantFiled: May 25, 2018Date of Patent: August 27, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert J. Allen, Yanai Danan, Vasant Rao, Jeffrey P. Soreff, Xin Zhao
-
Publication number: 20180373830Abstract: A method of performing transistor simulation with improved sensitivity to parasitic by model order reduction in transistor-level timing is disclosed. The method includes reducing a number of derivative calculations during transistor simulation by representing parasitics as a reduced-order model, wherein the reducing includes: compressing the parasitics to a reduced-order model; simulating with load which is replaced with the reduced-order model; differentiating results of the simulation with respect to reduced-order model parameters; differentiating parameters of the reduced-order model with respect to parasitic values; differentiating the parasitic values with respect to statistical parameters; and computing the differential results of the simulation with respect to the statistical parameters via chain ruling.Type: ApplicationFiled: May 25, 2018Publication date: December 27, 2018Inventors: Robert J. ALLEN, Yanai DANAN, Vasant RAO, Jeffrey P. SOREFF, Xin ZHAO
-
Patent number: 10031988Abstract: A method of performing transistor simulation with improved sensitivity to parasitic by model order reduction in transistor-level timing is disclosed. The method includes reducing a number of derivative calculations during transistor simulation by representing parasitics as a reduced-order model, wherein the reducing includes: compressing the parasitics to a reduced-order model; simulating with load which is replaced with the reduced-order model; differentiating results of the simulation with respect to reduced-order model parameters; differentiating parameters of the reduced-order model with respect to parasitic values; differentiating the parasitic values with respect to statistical parameters; and computing the differential results of the simulation with respect to the statistical parameters via chain ruling.Type: GrantFiled: September 24, 2014Date of Patent: July 24, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert J. Allen, Yanai Danan, Vasant Rao, Jeffrey P. Soreff, Xin Zhao
-
Patent number: 9690899Abstract: Methods of the present disclosure can include methods for prioritized path tracing in a statistical timing analysis of integrated circuits. Methods of the present disclosure can include: determining a required arrival time for a merge point in a statistical timing graph, the merge point having a plurality of associated input edges; calculating a plurality of edge slack distributions for each of the plurality of input edges and the required arrival time at the merge point; projecting a representative edge slack from each of the plurality of edge slack distributions; identifying a most critical input edge based on the plurality of representative edge slacks; generating a prioritized listing of input edges from lowest-value representative edge slack to highest-value representative edge slack; and tracing a next-most critical input edge of the prioritized listing, subsequent to tracing a path from the most critical edge to a source point.Type: GrantFiled: August 13, 2015Date of Patent: June 27, 2017Assignee: International Business Machines CorporationInventors: Vasant Rao, Debjit Sinha, Chandramouli Visweswariah
-
Publication number: 20170169148Abstract: A computer program product for improved modeling of differential circuits is provided. The computer program product includes a computer readable storage medium having program instructions embodied therewith. The program instructions are readable and executable by a processing circuit to cause the processing circuit to represent a configuration of a differential circuit on a defined space with representations of single-ended inputs and outputs disposed as differential input and output pairs along borders of the defined space, respectively, for each differential input and output pair, introduce an internal input or output differential node to feed from or to feed a corresponding differential input or output pair within the borders, respectively, with the internal input and output differential nodes being connectable and perform timing calculations with respect to input and output differential nodes.Type: ApplicationFiled: December 14, 2015Publication date: June 15, 2017Inventors: Hemlata Gupta, Jin Hu, Chad A. Marquart, Vasant Rao, Debjit Sinha
-
Patent number: 9659121Abstract: A computer program product for improved modeling of differential circuits is provided. The computer program product includes a computer readable storage medium having program instructions embodied therewith. The program instructions are readable and executable by a processing circuit to cause the processing circuit to represent a configuration of a differential circuit on a defined space with representations of single-ended inputs and outputs disposed as differential input and output pairs along borders of the defined space, respectively, for each differential input and output pair, introduce an internal input or output differential node to feed from or to feed a corresponding differential input or output pair within the borders, respectively, with the internal input and output differential nodes being connectable and perform timing calculations with respect to input and output differential nodes.Type: GrantFiled: December 14, 2015Date of Patent: May 23, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hemlata Gupta, Jin Hu, Chad A. Marquart, Vasant Rao, Debjit Sinha
-
Publication number: 20170046469Abstract: Methods of the present disclosure can include methods for prioritized path tracing in a statistical timing analysis of integrated circuits. Methods of the present disclosure can include: determining a required arrival time for a merge point in a statistical timing graph, the merge point having a plurality of associated input edges; calculating a plurality of edge slack distributions for each of the plurality of input edges and the required arrival time at the merge point; projecting a representative edge slack from each of the plurality of edge slack distributions; identifying a most critical input edge based on the plurality of representative edge slacks; generating a prioritized listing of input edges from lowest-value representative edge slack to highest-value representative edge slack; and tracing a next-most critical input edge of the prioritized listing, subsequent to tracing a path from the most critical edge to a source point.Type: ApplicationFiled: August 13, 2015Publication date: February 16, 2017Inventors: Vasant Rao, Debjit Sinha, Chandramouli Visweswariah
-
Publication number: 20160085890Abstract: A method of performing transistor simulation with improved sensitivity to parasitic by model order reduction in transistor-level timing is disclosed. The method includes reducing a number of derivative calculations during transistor simulation by representing parasitics as a reduced-order model, wherein the reducing includes: compressing the parasitics to a reduced-order model; simulating with load which is replaced with the reduced-order model; differentiating results of the simulation with respect to reduced-order model parameters; differentiating parameters of the reduced-order model with respect to parasitic values; differentiating the parasitic values with respect to statistical parameters; and computing the differential results of the simulation with respect to the statistical parameters via chain ruling.Type: ApplicationFiled: September 24, 2014Publication date: March 24, 2016Inventors: Robert J. ALLEN, Yanai DANAN, Vasant RAO, Jeffrey P. SOREFF, Xin ZHAO
-
Patent number: 8776004Abstract: Determining static timing analysis margin on non-controlling inputs of clock shaping and other digital circuits using reverse merge timing includes: selecting one or more circuits within the logic design having a plurality of inputs and using reverse merge; identifying a controlling input of the selected circuit from among this plurality of inputs; and determining for at least one non-controlling input of the circuit, a timing value that may be used to drive design optimization based on the difference between arrival times of the controlling and non-controlling inputs.Type: GrantFiled: January 14, 2011Date of Patent: July 8, 2014Assignee: International Business Machines CorporationInventors: Frank Borkam, Hemlata Gupta, David J. Hathaway, Kerim Kalafala, Vasant Rao, Alex Rubin
-
Patent number: 8655634Abstract: A system, method and program product for modeling load effects of a load CCC (channel connected component) in a transistor network. A system is disclosed that includes an analysis system that determines allowable logical state and transition functions for nets in a load CCC for a transition or state of a driving CCC for which a load condition is being determined; a trace system that traverses paths in the load CCC from a set of input terminals; and an element replacement system that replaces circuit elements in the load CCC to create a modeled CCC, wherein a circuit element replacement is based on a type of circuit element encountered along a trace, and state and transition functions of nets connected to an encountered circuit element.Type: GrantFiled: March 10, 2010Date of Patent: February 18, 2014Assignee: International Business Machines CorporationInventors: David J. Hathaway, Vasant Rao, Ronald D. Rose, Ali Sadigh, Jeffrey P. Soreff, David W. Winston
-
Publication number: 20120185810Abstract: Determining static timing analysis margin on non-controlling inputs of clock shaping and other digital circuits using reverse merge timing includes: selecting one or more circuits within the logic design having a plurality of inputs and using reverse merge; identifying a controlling input of the selected circuit from among this plurality of inputs; and determining for at least one non-controlling input of the circuit, a timing value that may be used to drive design optimization based on the difference between arrival times of the controlling and non-controlling inputs.Type: ApplicationFiled: January 14, 2011Publication date: July 19, 2012Applicant: International Business Machines CorporationInventors: Frank Borkam, Hemlata Gupta, David J. Hathaway, Kerim Kalafala, Vasant Rao, Alex Rubin
-
Patent number: 8201120Abstract: A method and a system for selecting timing points in an electrical interconnect network to be used in electrical simulations for a static timing analysis for improved accuracy. The present method includes discovering choke points in an electrical model of the interconnect for which all the paths from drivers to receivers must pass through on certain types of nets. The method then uses the choke point electrical nodes, where they exist, as an output timing point of the logic gate driving the net. The method solves the problem of inaccuracies due to resistances between different driver pins on the same interconnect net, though it can also be applied to solving analogous inaccuracies due to resistances between different receiver pins associated with the same receiver timing point.Type: GrantFiled: January 5, 2010Date of Patent: June 12, 2012Assignee: International Business Machines CorporationInventors: Jeffrey P. Soreff, Barry Lee Dorfman, Jeffrey G. Hemmett, Ravichander Ledalla, Vasant Rao, Fred Lei Yang
-
Patent number: 8112735Abstract: A computer system for partitioning the columns of a matrix A. The computer system includes a processor and a memory unit coupled to the processor. Program code in the memory unit, when executed by the processor, implements the method. Matrix A is provided in a memory device and has n columns and m rows; wherein n is an integer of at least 3; and wherein m is an integer of at least 1. The n columns is partitioned into a closed group of p clusters, p being a positive integer of at least 2 and less than n. The partitioning includes an affinity -based merging of clusters of pairs of clusters of the matrix A based on an affinity between the clusters in each pair of clusters being merged. Each cluster consists of one or more columns of matrix A. The p clusters are stored in a computer-readable storage device.Type: GrantFiled: January 28, 2008Date of Patent: February 7, 2012Assignee: International Business Machines CorporationInventors: Kerim Kalafala, Vasant Rao, Chandramouli Visweswariah