Abstract: An apparatus and method for implementing synchronous triggers for waveform capture in a multiple FPGA system is described. The apparatus includes trigger net circuitry that has one or more trigger nets and an output. Furthermore, a plurality of programmable logic devices are provided with each logic device including logic circuitry that is programmable to correspond to a circuit design, a logic analyzer circuit that includes logic connections coupled to the logic circuitry to monitor operating signals of the circuit design, and a register with a data input that is coupled to the output of the trigger net circuitry and an output that is coupled to a control input of the logic analyzer circuit. The trigger net circuitry outputs a control signal that is applied to all registers such that each logic analyzer circuit is controlled to concurrently capture data waveforms.

Abstract: An apparatus and method for fast phase aligned local generation of design clocks on a multiple FPGA system via clock generator replication is described. The apparatus includes a reference clock that generates a clock signal have a reference frequency and a plurality of programmable logic devices. Each programmable logic device includes phase locked loop circuitry that receives the clock signal from the reference clock and generates a local reference clock signal having a frequency based on the reference frequency and a clock generator that receives the local reference clock signal and generates local design clocks based on the local reference clock signal. Because each local design clock generator is synchronized by the same reference clock over a low skew line, the edges of the local design clocks are aligned.

Abstract: An apparatus and method is described for low skew phase generation for multiplexing signals using limited global low skew lines on a multiple FPGA system. The apparatus includes a reference clock programmed to generate a clock signal and programmable logic devices. The programmable logic devices include I/O terminals, combinational logic coupled to the I/O terminals, programmable logic coupled to the combinational logic, a phase generator programmed to receive the clock signal from the reference clock and to generate a phase clock based on the clock signal and a plurality of phase enable signals based on the phase clock, low skew lines to distribute the phase enables with minimal skew caused by routing delays, and flip-flops programmed to have a clock input driven by the phase clock, a data input coupled to ground, and a data output coupled to the combinational logic.