Patents by Inventor Vasantha K. Erraguntla
Vasantha K. Erraguntla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8577948Abstract: In one embodiment, a processor includes a multiply-accumulate (MAC) unit having a first path to handle execution of an instruction if a difference between at least a portion of first and second operands and a third operand is less than a threshold value, and a second path to handle the instruction execution if the difference is greater than the threshold value. Based on the difference, at least part of the third operand is to be provided to a multiplier of the MAC unit or to a compressor of the second path. Other embodiments are described and claimed.Type: GrantFiled: September 20, 2010Date of Patent: November 5, 2013Assignee: Intel CorporationInventors: Suresh Srinivasan, Rajaraman Ramanarayanan, Sanu K. Mathew, Ram K. Krishnamurthy, Vasantha K. Erraguntla
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Patent number: 8214414Abstract: A merged datapath for PopCount and BitScan is described. A hardware circuit includes a compressor tree utilized for a PopCount function, which is reused by a BitScan function (e.g., bit scan forward (BSF) or bit scan reverse (BSR)). Selector logic enables the compressor tree to operate on an input word for the PopCount or BitScan operation, based on a microprocessor instruction. The input word is encoded if a BitScan operation is selected. The compressor tree receives the input word, operates on the bits as though all bits have same level of significance (e.g., for an N-bit input word, the input word is treated as N one-bit inputs). The result of the compressor tree circuit is a binary value representing a number related to the operation performed (the number of set bits for PopCount, or the bit position of the first set bit encountered by scanning the input word).Type: GrantFiled: September 30, 2008Date of Patent: July 3, 2012Assignee: Intel CorporationInventors: Rajaraman Ramanarayanan, Sanu K. Mathew, Ram K. Krishnamurthy, Shay Gueron, Vasantha K. Erraguntla
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Publication number: 20120072703Abstract: In one embodiment, a processor includes a multiply-accumulate (MAC) unit having a first path to handle execution of an instruction if a difference between at least a portion of first and second operands and a third operand is less than a threshold value, and a second path to handle the instruction execution if the difference is greater than the threshold value. Based on the difference, at least part of the third operand is to be provided to a multiplier of the MAC unit or to a compressor of the second path. Other embodiments are described and claimed.Type: ApplicationFiled: September 20, 2010Publication date: March 22, 2012Inventors: SURESH SRINIVASAN, RAJARAM RAMANARAYANAN, SANU K. MATHEW, RAM K. KRISHNAMURTHY, VASANTHA K. ERRAGUNTLA
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Publication number: 20100082718Abstract: A merged datapath for PopCount and BitScan is described. A hardware circuit includes a compressor tree utilized for a PopCount function, which is reused by a BitScan function (e.g., bit scan forward (BSF) or bit scan reverse (BSR)). Selector logic enables the compressor tree to operate on an input word for the PopCount or BitScan operation, based on a microprocessor instruction. The input word is encoded if a BitScan operation is selected. The compressor tree receives the input word, operates on the bits as though all bits have same level of significance (e.g., for an N-bit input word, the input word is treated as N one-bit inputs). The result of the compressor tree circuit is a binary value representing a number related to the operation performed (the number of set bits for PopCount, or the bit position of the first set bit encountered by scanning the input word).Type: ApplicationFiled: September 30, 2008Publication date: April 1, 2010Applicant: Intel CorporationInventors: Rajaraman Ramanarayanan, Sanu K. Mathew, Ram K. Krishnamurthy, Shay Gueron, Vasantha K. Erraguntla
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Patent number: 7668165Abstract: Methods and apparatus for processing transmission control protocol (TCP) packets using hardware-based multi-threading techniques. Inbound and outbound TCP packet are processed using a multi-threaded TCP offload engine (TOE). The TOE includes an execution core comprising a processing engine, a scheduler, an on-chip cache, a host memory interface, a host interface, and a network interface controller (NIC) interface. In one embodiment, the TOE is embodied as a memory controller hub (MCH) component of a platform chipset. The TOE may further include an integrated direct memory access (DMA) controller, or the DMA controller may be embodied as separate circuitry on the MCH. In one embodiment, inbound packets are queued in an input buffer, the headers are provided to the scheduler, and the scheduler arbitrates thread execution on the processing engine. Concurrently, DMA payload data transfers are queued and asynchronously performed in a manner that hides memory latencies.Type: GrantFiled: March 31, 2004Date of Patent: February 23, 2010Assignee: Intel CorporationInventors: Yatin Hoskote, Sriram R. Vangal, Vasantha K. Erraguntla, Nitin Y. Borkar
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Patent number: 7324540Abstract: The disclosure describes techniques for coordinating operation of multiple network protocol off-load engines (e.g., Transport Control Protocol (TCP) off-load engines).Type: GrantFiled: December 31, 2002Date of Patent: January 29, 2008Assignee: Intel CorporationInventors: Sriram R. Vangal, Yatin Hoskote, Vasantha K. Erraguntla, Jianping Xu
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Patent number: 7181544Abstract: Packet processing techniques that can be used, for example, by a network protocol off-load engine. For example, the techniques may be used in an engine that performs transmission control protocol (TCP) operations for received packets for a host.Type: GrantFiled: September 3, 2002Date of Patent: February 20, 2007Assignee: Intel CorporationInventors: Sriram R. Vangal, Yatin Hoskote, Nitin Y. Borkar, Jianping Xu, Vasantha K. Erraguntla, Shekhar Y. Borkar
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Patent number: 7016354Abstract: In general, in one aspect, the disclosure describes a method for use in packet processing. The method can include receiving at least a portion of at least one packet and, based on the at least a portion of the at least one packet, determining a clock signal to provide to processing logic that processes the at least one packet.Type: GrantFiled: September 3, 2002Date of Patent: March 21, 2006Assignee: Intel CorporationInventors: Sriram R. Vangal, Yatin Hoskote, Nitin Y. Borkar, Jianping Xu, Vasantha K. Erraguntla, Shekhar Y. Borkar
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Publication number: 20040193733Abstract: The disclosure describes packet processing techniques that can be used, for example, by a network protocol off-load engine. For example, the techniques may be used in an engine that performs transmission control protocol (TCP) operations for received packets for a host.Type: ApplicationFiled: September 3, 2002Publication date: September 30, 2004Inventors: Sriram R. Vangal, Yatin Hoskote, Nitin Y. Borkar, Jianping Xu, Vasantha K. Erraguntla, Shekhar Y. Borkar
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Publication number: 20040125751Abstract: The disclosure describes techniques for coordinating operation of multiple network protocol off-load engines (e.g., Transport Control Protocol (TCP) off-load engines).Type: ApplicationFiled: December 31, 2002Publication date: July 1, 2004Inventors: Sriram R. Vangal, Yatin Hoskote, Vasantha K. Erraguntla, Jianping Xu
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Publication number: 20040042497Abstract: In general, in one aspect, the disclosure describes a method for use in packet processing. The method can include receiving at least a portion of at least one packet and, based on the at least a portion of the at least one packet, determining a clock signal to provide to processing logic that processes the at least one packet.Type: ApplicationFiled: September 3, 2002Publication date: March 4, 2004Inventors: Sriram R. Vangal, Yatin Hoskote, Nitin Y. Borkar, Jianping Xu, Vasantha K. Erraguntla, Shekhar Y. Borkar