Abstract: A semiconductor device includes a substrate, one or more transistors, a metal layer, one or more buried power rails, and at least one wall-via structure. The transistors and the metal layer are manufactured above a top surface of the substrate. The buried power rails are in one or more corresponding trenches in the substrate below the top surface of the substrate. At least one wall-via structure extends between the first buried power rail and the metal layer and electrically connects the first buried power rail to the metal layer. The wall-via structure includes a plurality of intermediate metal layers sandwiched between the first buried power rail and the metal layer. Alternatively, the wall-via structure includes a length that is greater than or equal to four times a basic length unit for components in layers between the first buried power rail and the metal layer for the semiconductor device.

Abstract: A semiconductor device includes a substrate, one or more transistors, a metal layer, one or more buried power rails, and at least one wall-via structure. The transistors and the metal layer are manufactured above a top surface of the substrate. The buried power rails are in one or more corresponding trenches in the substrate below the top surface of the substrate. At least one wall-via structure extends between the first buried power rail and the metal layer and electrically connects the first buried power rail to the metal layer. The wall-via structure includes a plurality of intermediate metal layers sandwiched between the first buried power rail and the metal layer. Alternatively, the wall-via structure includes a length that is greater than or equal to four times a basic length unit for components in layers between the first buried power rail and the metal layer for the semiconductor device.

Abstract: A semiconductor device includes a substrate, one or more transistors, a metal layer, one or more buried power rails, and at least one wall-via structure. The transistors and the metal layer are manufactured above a top surface of the substrate. The buried power rails are in one or more corresponding trenches in the substrate below the top surface of the substrate. At least one wall-via structure extends between the first buried power rail and the metal layer and electrically connects the first buried power rail to the metal layer. The wall-via structure includes a plurality of intermediate metal layers sandwiched between the first buried power rail and the metal layer. Alternatively, the wall-via structure includes a length that is greater than or equal to four times a basic length unit for components in layers between the first buried power rail and the metal layer for the semiconductor device.

Abstract: A semiconductor device includes a substrate, one or more transistors, a metal layer, one or more buried power rails, and at least one wall-via structure. The transistors and the metal layer are manufactured above a top surface of the substrate. The buried power rails are in one or more corresponding trenches in the substrate below the top surface of the substrate. At least one wall-via structure extends between the first buried power rail and the metal layer and electrically connects the first buried power rail to the metal layer. The wall-via structure includes a plurality of intermediate metal layers sandwiched between the first buried power rail and the metal layer. Alternatively, the wall-via structure includes a length that is greater than or equal to four times a basic length unit for components in layers between the first buried power rail and the metal layer for the semiconductor device.

Abstract: A flip-flop includes a gate circuit and five logic gates. The gate circuit receives as inputs a data input d, an intermediate signal p, a control signal si and a control signal se, and outputs an intermediate signal pb. A first logic gate receives as inputs the intermediate signal pb, an intermediate signal cb, and outputs an intermediate signal c. A second logic gate receives as inputs a clock signal clk and the intermediate signal c, and outputs the intermediate signal cb. The third logic gate receives as inputs the clock signal clk, the intermediate signal p, the intermediate signal cb, and outputs the intermediate signal p. The fourth logic gate receives as inputs the intermediate signal cb and a signal qb, and outputs a signal q. The fifth logic gate receives as inputs the intermediate signal p and first signal q, and outputs the signal qb.

Abstract: A digital signal processing block with a preadder stage for an integrated circuit is described. The digital signal processing block includes a preadder stage and a control bus. The control bus is coupled to the preadder stage for dynamically controlling operation of the preadder stage. The preadder stage includes: a first input port of a first multiplexer coupled to the control bus; a second input port of a first logic gate coupled to the control bus; a third input port of a second logic gate coupled to the control bus; and a fourth input port of an adder/subtractor coupled to the control bus.

Abstract: A computer-implemented method of identifying timing paths of a circuit block can include representing a circuit block including at least one bypassable component as a block diagram having a plurality of elements linked by nodes. The method can include generating a map file including a text description of each element within the block diagram, wherein the text description of each element specifies a bypass indicator for the element. The method also can include generating a plurality of sub-paths from the map file, determining timing paths from the plurality of sub-paths by selectively combining different ones of the plurality of sub-paths according to commonality of starting points and ending points of the plurality of sub-paths, and outputting the timing paths.

Abstract: A digital signal processing block with a preadder stage for an integrated circuit is described. The digital signal processing block includes a preadder stage and a control bus. The control bus is coupled to the preadder stage for dynamically controlling operation of the preadder stage. The preadder stage includes: a first input port of a first multiplexer coupled to the control bus; a second input port of a first logic gate coupled to the control bus; a third input port of a second logic gate coupled to the control bus; and a fourth input port of an adder/subtractor coupled to the control bus.

Abstract: Method and apparatus for data monitoring for error detection is described. A programmable logic device includes a configurable logic block having function generators, each of which is configurable for at least two programmable mode functions. The function generators are coupled to an array of memory cells for storing configuration bits for configuring the function generators. A primary address line is coupled to each memory cell spanning two or more of the function generators. A secondary address line is coupled to groups of memory cells associated with the function generators. A mask circuit is configured to selectively communicate a signal of the primary address line to a segment of the secondary address line or to a ground responsive in part to the program mode function.

Abstract: One or more configurable transceivers can be fabricated on an integrated circuit. The transceivers contain various components having options that can be configured by turning configuration memory cells on or off. The integrated circuit may also contain programmable fabric. Other components in the transceivers can have options that are controlled by the programmable fabric. The integrated circuit may also contain one or more processor cores. The processor core and the transceivers can be connected by a plurality of signal paths that pass through the programmable fabric.

Abstract: Method and apparatus for data monitoring for error detection is described. A programmable logic device includes a configurable logic block having function generators, each of which is configurable for at least two programmable mode functions. The function generators are coupled to an array of memory cells for storing configuration bits for configuring the function generators. A primary address line is coupled to each memory cell spanning two or more of the function generators. A secondary address line is coupled to groups of memory cells associated with the function generators. A mask circuit is configured to selectively communicate a signal of the primary address line to a segment of the secondary address line or to a ground responsive in part to the program mode function.

Abstract: Described are glitchless clock control circuits capable of switching away from a failed clock. One embodiment supports three basic functions: clock select, clock enable, and clock ignore. The clock-select function provides a selected one of a plurality of clock signals on a clock-distribution node. The select signals used to switch between clock signals need to be synchronous with any of the clock signals. The clock-enable function allows the clock control circuit to synchronously block or pass a selected clock signal. Finally, the clock-ignore function allows the clock control circuit to ignore a selected clock if necessary, for example, to switch away from a failed clock.

Abstract: A programmable logic device (PLD) is provided that supports multi-gigabit transceivers (MGTs). The PLD includes one or more pairs of shared clock pads for receiving one or more high-quality differential clock signals. Dedicated clock traces couple each pair of shared clock pads to one or more MGTs on the PLD. Each MGT includes a clock multiplexer circuit, which allows one of the high-quality differential clock signals to be routed as a reference clock signal for the MGT. The clock multiplexer circuits are designed such that no significant jitter is added to the high-quality clock signals. The clock multiplexer circuits can also route general-purpose clock signals received by the PLD as lower quality reference clock signals for the MGTs. The reference clock signal routed by the clock multiplexer circuit can be stepped down to provide a reference clock for a physical coding sublayer of the MGT.