Patents by Inventor Vason P. Srini

Vason P. Srini has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9768797
    Abstract: Methods and apparatus, including computer program products, are provided for receivers. In one aspect there is provided an apparatus. The apparatus may include an in-phase sigma delta receiver coupled to a radio frequency input port providing at least a first carrier aggregation signal and a second carrier aggregation signal; and a quadrature phase sigma delta receiver coupled to the radio frequency input port providing at least the first carrier aggregation signal and the second aggregation signal, wherein the in-phase sigma delta receiver and the quadrature phase sigma delta receiver each include a resonator stage circuitry including at least one variable capacitor that varies notch frequencies to provide passbands for the first carrier aggregation signal and the second carrier aggregation signal. Related apparatus, systems, methods, and articles are also described.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: September 19, 2017
    Assignee: Nokia Technologies Oy
    Inventors: Chadi Jabbour, Seyed Majid Homayouni, Sudhir Aggarwal, Vason P. Srini
  • Patent number: 9634702
    Abstract: Methods and apparatus, including computer program products, are provided for receivers. In one aspect there is provided an apparatus. In some example embodiments, there is provided an apparatus. The apparatus may include a first N-path filter configured with at least a first passband, wherein the first N-path filter is coupled to a radio frequency input port providing at least a first carrier aggregation signal, a second carrier aggregation signal, and an interfering signal; a second N-path filter configured with at least a second passband, wherein the second N-path filter is coupled to the radio frequency input port providing at least the first carrier aggregation signal, the second carrier aggregation signal, and the interfering signal; and a combiner configured to subtract a first output of the first N-path filter from a second output of the second N-path filter. Related apparatus, systems, methods, and articles are also described.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: April 25, 2017
    Assignee: Nokia Technologies Oy
    Inventors: Chadi Jabbour, Sudhir Aggarwal, Vason P. Srini
  • Publication number: 20160322996
    Abstract: Methods and apparatus, including computer program products, are provided for receivers. In one aspect there is provided an apparatus. In some example embodiments, there is provided an apparatus. The apparatus may include a first N-path filter configured with at least a first passband, wherein the first N-path filter is coupled to a radio frequency input port providing at least a first carrier aggregation signal, a second carrier aggregation signal, and an interfering signal; a second N-path filter configured with at least a second passband, wherein the second N-path filter is coupled to the radio frequency input port providing at least the first carrier aggregation signal, the second carrier aggregation signal, and the interfering signal; and a combiner configured to subtract a first output of the first N-path filter from a second output of the second N-path filter. Related apparatus, systems, methods, and articles are also described.
    Type: Application
    Filed: November 3, 2015
    Publication date: November 3, 2016
    Inventors: Chadi Jabbour, Sudhir Aggarwal, Vason P. Srini
  • Publication number: 20160269042
    Abstract: Methods and apparatus, including computer program products, are provided for receivers. In one aspect there is provided an apparatus. The apparatus may include an in-phase sigma delta receiver coupled to a radio frequency input port providing at least a first carrier aggregation signal and a second carrier aggregation signal; and a quadrature phase sigma delta receiver coupled to the radio frequency input port providing at least the first carrier aggregation signal and the second aggregation signal, wherein the in-phase sigma delta receiver and the quadrature phase sigma delta receiver each include a resonator stage circuitry including at least one variable capacitor that varies notch frequencies to provide passbands for the first carrier aggregation signal and the second carrier aggregation signal. Related apparatus, systems, methods, and articles are also described.
    Type: Application
    Filed: November 3, 2015
    Publication date: September 15, 2016
    Inventors: Chadi Jabbour, Seyed Majid Homayouni, Sudhir Aggarwal, Vason P. Srini
  • Patent number: 5053942
    Abstract: A cross-connect circuit for coupling each of a plurality of processors to a memory module selected from a plurality of such modules, provided the module in question has not been identified for connection to another of the processors is disclosed. The circuit is preferably organized as a bit-sliced chip. The connections made by the cross-connect circuit can be changed after each memory cycle.
    Type: Grant
    Filed: November 1, 1988
    Date of Patent: October 1, 1991
    Assignee: The Regents of the University of California
    Inventor: Vason P. Srini