Patents by Inventor Vassilios Gerousis
Vassilios Gerousis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230104185Abstract: A semiconductor cell block includes a series of layers arranged in a stack. The layers include one or more first layers each having a first height and one or more second layers each having a second height. The second height is larger than the first height, and the second height is a non-integer multiple of the first height. The semiconductor cell block also includes a first semiconductor logic cell having a first cell height in one of the series of layers, and a second semiconductor logic cell having a second cell height in one of the series of layers. The second cell height is larger than the first cell height, and the second cell height is a non-integer value multiple of the first cell height.Type: ApplicationFiled: October 20, 2022Publication date: April 6, 2023Inventors: Vassilios Gerousis, Rwik Sengupta, Joon Goo Hong, Kevin Traynor, Tanya Abaya, Dharmendar Palle, Mark S. Rodder
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Patent number: 11605574Abstract: A monolithic three-dimensional integrated circuit including a first device, a second device on the first device, and a thermal shield stack between the first device and the second device. The thermal shield stack includes a thermal retarder portion having a low thermal conductivity in a vertical direction, and a thermal spreader portion having a high thermal conductivity in a horizontal direction. The thermal shield stack of the monolithic three-dimensional integrated circuit includes only dielectric materials.Type: GrantFiled: March 2, 2021Date of Patent: March 14, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Wei-E Wang, Mark S. Rodder, Vassilios Gerousis
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Patent number: 11552067Abstract: A semiconductor cell block includes a series of layers arranged in a stack. The layers include one or more first layers each having a first height and one or more second layers each having a second height. The second height is larger than the first height, and the second height is a non-integer multiple of the first height. The semiconductor cell block also includes a first semiconductor logic cell having a first cell height in one of the series of layers, and a second semiconductor logic cell having a second cell height in one of the series of layers. The second cell height is larger than the first cell height, and the second cell height is a non-integer value multiple of the first cell height.Type: GrantFiled: April 20, 2020Date of Patent: January 10, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Vassilios Gerousis, Rwik Sengupta, Joon Goo Hong, Kevin Traynor, Tanya Abaya, Dharmendar Palle, Mark S. Rodder
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Patent number: 11189600Abstract: A method of manufacturing a three-dimensional semiconductor device includes forming a bi-layer sacrificial stack on a top wafer and a bottom wafer each including a series of interconnects in a dielectric substrate. The bi-layer sacrificial stack includes a second sacrificial layer on a first sacrificial layer. The method also includes selectively etching the second sacrificial layers to form a first pattern of projections on the top wafer and a second pattern of projections on the bottom wafer. The first pattern of projections is configured to mesh with the second pattern of projections. The method also includes positioning the top wafer on the bottom wafer and releasing the top wafer such that engagement between the first pattern of projections and the second pattern of projections self-aligns the plurality of interconnects of the top wafer with the plurality of interconnects of the bottom wafer within a misalignment error.Type: GrantFiled: April 28, 2020Date of Patent: November 30, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Wei-E Wang, Mark S. Rodder, Vassilios Gerousis
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Patent number: 11158738Abstract: A method of forming a stacked field effect transistor (FET) circuit is provided. The method includes providing a first wafer and a second wafer, forming a first dielectric layer on a surface of the first wafer, forming a second dielectric layer on a surface of the second wafer, and bonding the first wafer to the second wafer at the first dielectric layer and the second dielectric layer.Type: GrantFiled: August 22, 2019Date of Patent: October 26, 2021Inventors: Wei-E Wang, Mark Rodder, Vassilios Gerousis
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Publication number: 20210265334Abstract: A semiconductor cell block includes a series of layers arranged in a stack. The layers include one or more first layers each having a first height and one or more second layers each having a second height. The second height is larger than the first height, and the second height is a non-integer multiple of the first height. The semiconductor cell block also includes a first semiconductor logic cell having a first cell height in one of the series of layers, and a second semiconductor logic cell having a second cell height in one of the series of layers. The second cell height is larger than the first cell height, and the second cell height is a non-integer value multiple of the first cell height.Type: ApplicationFiled: April 20, 2020Publication date: August 26, 2021Inventors: Vassilios Gerousis, Rwik Sengupta, Joon Goo Hong, Kevin Traynor, Tanya Abaya, Dharmendar Palle, Mark S. Rodder
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Publication number: 20210183729Abstract: A monolithic three-dimensional integrated circuit including a first device, a second device on the first device, and a thermal shield stack between the first device and the second device. The thermal shield stack includes a thermal retarder portion having a low thermal conductivity in a vertical direction, and a thermal spreader portion having a high thermal conductivity in a horizontal direction. The thermal shield stack of the monolithic three-dimensional integrated circuit includes only dielectric materials.Type: ApplicationFiled: March 2, 2021Publication date: June 17, 2021Inventors: Wei-E Wang, Mark S. Rodder, Vassilios Gerousis
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Publication number: 20210183814Abstract: A method of manufacturing a three-dimensional semiconductor device includes forming a bi-layer sacrificial stack on a top wafer and a bottom wafer each including a series of interconnects in a dielectric substrate. The bi-layer sacrificial stack includes a second sacrificial layer on a first sacrificial layer. The method also includes selectively etching the second sacrificial layers to form a first pattern of projections on the top wafer and a second pattern of projections on the bottom wafer. The first pattern of projections is configured to mesh with the second pattern of projections. The method also includes positioning the top wafer on the bottom wafer and releasing the top wafer such that engagement between the first pattern of projections and the second pattern of projections self-aligns the plurality of interconnects of the top wafer with the plurality of interconnects of the bottom wafer within a misalignment error.Type: ApplicationFiled: April 28, 2020Publication date: June 17, 2021Inventors: Wei-E Wang, Mark S. Rodder, Vassilios Gerousis
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Patent number: 10971420Abstract: A monolithic three-dimensional integrated circuit including a first device, a second device on the first device, and a thermal shield stack between the first device and the second device. The thermal shield stack includes a thermal retarder portion having a low thermal conductivity in a vertical direction, and a thermal spreader portion having a high thermal conductivity in a horizontal direction. The thermal shield stack of the monolithic three-dimensional integrated circuit includes only dielectric materials.Type: GrantFiled: April 3, 2019Date of Patent: April 6, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Wei-E Wang, Mark S. Rodder, Vassilios Gerousis
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Patent number: 10886224Abstract: A tap cell configured to enable electrical connection from a buried power rail of an integrated circuit to a power distribution network includes. The tap cell includes a buried power rail layer including VDD and VSS power supply lines, insulating layers and metal layers alternately arranged on the buried power rail layer, a first power supply interconnect in metal layer M1 or higher electrically coupled to the VDD power supply line, and a second power supply interconnect in metal layer M1 or higher electrically connected to the VSS power supply line. The first power supply interconnect and the second power supply interconnect are configured to be electrically connected to the power distribution network, and the VDD and VSS power supply lines are configured to supply power from the power distribution network to the buried power rail of the integrated circuit. The tap cell is free of any active semiconductor devices.Type: GrantFiled: September 5, 2019Date of Patent: January 5, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Vassilios Gerousis, Rwik Sengupta, Joon Goo Hong, Kevin Michael Traynor
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Publication number: 20200403097Abstract: A method of forming a stacked field effect transistor (FET) circuit is provided. The method includes providing a first wafer and a second wafer, forming a first dielectric layer on a surface of the first wafer, forming a second dielectric layer on a surface of the second wafer, and bonding the first wafer to the second wafer at the first dielectric layer and the second dielectric layer.Type: ApplicationFiled: August 22, 2019Publication date: December 24, 2020Inventors: Wei-E WANG, Mark RODDER, Vassilios GEROUSIS
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Publication number: 20200373241Abstract: A tap cell configured to enable electrical connection from a buried power rail of an integrated circuit to a power distribution network includes. The tap cell includes a buried power rail layer including VDD and VSS power supply lines, insulating layers and metal layers alternately arranged on the buried power rail layer, a first power supply interconnect in metal layer M1 or higher electrically coupled to the VDD power supply line, and a second power supply interconnect in metal layer M1 or higher electrically connected to the VSS power supply line. The first power supply interconnect and the second power supply interconnect are configured to be electrically connected to the power distribution network, and the VDD and VSS power supply lines are configured to supply power from the power distribution network to the buried power rail of the integrated circuit. The tap cell is free of any active semiconductor devices.Type: ApplicationFiled: September 5, 2019Publication date: November 26, 2020Inventors: Vassilios Gerousis, Rwik Sengupta, Joon Goo Hong, Kevin Michael Traynor
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Patent number: 10811415Abstract: According to some example embodiments of the present disclosure, a semiconductor device includes: a substrate; a first semiconductor layer over the substrate, the first semiconductor layer being a first type of semiconductor device; and a second semiconductor layer over the substrate and the first semiconductor layer, the second semiconductor layer being the first type of semiconductor device, wherein a first portion of the first semiconductor layer overlaps the second semiconductor layer when viewed in a direction perpendicular to a plane of the substrate and a second portion of the first semiconductor layer is laterally offset from the second semiconductor layer when viewed in the direction perpendicular to the plane of the substrate.Type: GrantFiled: March 11, 2019Date of Patent: October 20, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Rwik Sengupta, Joon Goo Hong, Vassilios Gerousis, Mark S. Rodder
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Publication number: 20200203247Abstract: A monolithic three-dimensional integrated circuit including a first device, a second device on the first device, and a thermal shield stack between the first device and the second device. The thermal shield stack includes a thermal retarder portion having a low thermal conductivity in a vertical direction, and a thermal spreader portion having a high thermal conductivity in a horizontal direction. The thermal shield stack of the monolithic three-dimensional integrated circuit includes only dielectric materials.Type: ApplicationFiled: April 3, 2019Publication date: June 25, 2020Inventors: Wei-E Wang, Mark S. Rodder, Vassilios Gerousis
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Publication number: 20200201954Abstract: A computer-implemented method includes generating a layout of a semiconductor cell. The layout includes a series of semiconductor devices, intra-cell connections, including power rails, between the plurality of semiconductor devices, and a series of shadow pin regions for placement of a series of pins by a placement and routing tool. Each shadow pin region of the series of shadow pin regions defines a maximum legal boundary that each pin of the series of pins may occupy without violating ground rules.Type: ApplicationFiled: March 27, 2019Publication date: June 25, 2020Inventors: Vassilios Gerousis, Rwik Sengupta
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Publication number: 20200135735Abstract: According to some example embodiments of the present disclosure, a semiconductor device includes: a substrate; a first semiconductor layer over the substrate, the first semiconductor layer being a first type of semiconductor device; and a second semiconductor layer over the substrate and the first semiconductor layer, the second semiconductor layer being the first type of semiconductor device, wherein a first portion of the first semiconductor layer overlaps the second semiconductor layer when viewed in a direction perpendicular to a plane of the substrate and a second portion of the first semiconductor layer is laterally offset from the second semiconductor layer when viewed in the direction perpendicular to the plane of the substrate.Type: ApplicationFiled: March 11, 2019Publication date: April 30, 2020Inventors: Rwik Sengupta, Joon Goo Hong, Vassilios Gerousis, Mark S. Rodder
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Patent number: 9286432Abstract: Disclosed are methods, systems, and articles of manufactures for implementing correct-by-construction physical designs with multiple-patterning-awareness by identifying a first set of grids for a layer based at least in part upon characteristics of other layer(s), identifying a set of tracks for the layer to implement the physical design for the layer, and implementing a shape in the physical design by at least terminating an end of the shape at a grid of the identified first set of grids. The end of the shape may be extended or contracted from its as-design location to the grid. The physical design thus implemented is correct-by-construction and is free of violations of one or more directional design rules.Type: GrantFiled: March 15, 2013Date of Patent: March 15, 2016Assignee: Cadence Design Systems, Inc.Inventors: Vassilios Gerousis, Shuo Zhang, Stefanus Mantik, Yuan Huang, Jing Chen, Jianmin Li
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Patent number: 9245076Abstract: Various embodiments include computer-implemented methods, computer program products and systems for aligning a set of orthogonal circuit elements in an integrated circuit (IC) layout. In some embodiments, a computer-implemented method for aligning a set of orthogonal circuit elements in an IC layout includes: classifying each orthogonal circuit element in the set of orthogonal circuit elements as including a first space-designated edge and a second space-designated edge; and aligning each orthogonal circuit element on an edge placement grid according to the first space-designated edge and the second space-designated edge, the edge placement grid having a first set of space-designated grid lines separated by a first distance, and a second set of space-designated grid lines separated by a second distance, wherein the first set of space-designated grid lines is separated from the second set of space-designated grid lines by an offset distance.Type: GrantFiled: June 3, 2013Date of Patent: January 26, 2016Assignee: International Business Machines CorporationInventors: Vassilios Gerousis, Lars W. Liebmann, Stefanus Mantik, Gustavo E. Tellez, Shuo Zhang
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Patent number: 9087174Abstract: Disclosed are methods, systems, and articles of manufactures for implementing multiple-patterning-aware design rule check for an electronic design. Various embodiments identify one or more sets of multiple-exposure grids and identify or generate a data structure by using the one or more sets of grids to store design data of shape ends of various ends. Various embodiments perform constant time design rule checking by performing a constant time search process on the data structure to look up from the data structure one or more violations of one or more design rules which include at least one directional design rule. Some aspects are directed at fixing a design rule violation by using at least some grids of the one or more sets of grids.Type: GrantFiled: March 15, 2013Date of Patent: July 21, 2015Assignee: Cadence Design Systems, Inc.Inventors: Shuo Zhang, Vassilios Gerousis
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Publication number: 20140359548Abstract: Various embodiments include computer-implemented methods, computer program products and systems for aligning a set of orthogonal circuit elements in an integrated circuit (IC) layout. In some embodiments, a computer-implemented method for aligning a set of orthogonal circuit elements in an IC layout includes: classifying each orthogonal circuit element in the set of orthogonal circuit elements as including a first space-designated edge and a second space-designated edge; and aligning each orthogonal circuit element on an edge placement grid according to the first space-designated edge and the second space-designated edge, the edge placement grid having a first set of space-designated grid lines separated by a first distance, and a second set of space-designated grid lines separated by a second distance, wherein the first set of space-designated grid lines is separated from the second set of space-designated grid lines by an offset distance.Type: ApplicationFiled: June 3, 2013Publication date: December 4, 2014Inventors: Vassilios Gerousis, Lars W. Liebmann, Stefanus Mantik, Gustavo E. Tellez, Shuo Zhang