Abstract: Described is an apparatus which comprises: a first voltage regulator (VR) having a reference input node; and a first multiplexer to provide a reference voltage to the reference input node and operable to select one of at least two different reference voltages as the reference voltage.

Abstract: Power management circuitry may be provided to control a power state of a voltage regulator for providing a regulated voltage to a load, the voltage regulator being operable in at least first and second different power states. The power management circuitry may comprise circuitry to determine output current data relating to an output current to be provided by the voltage regulator to the load. The power management circuitry may comprise circuitry to determine regulated voltage data relating to a regulated voltage to be provided by the voltage regulator to the load. The power management circuitry may comprise circuitry to cause a change in the power state of the voltage regulator from the first power state to the second power state based on a comparison of the determined output current data and power state current threshold data.

Abstract: In one embodiment, a processor includes: at least one core to execute a workload; a voltage regulator to provide an operating voltage to the at least one core; and a power controller coupled to the voltage regulator. The power controller may control the voltage regulator to provide the operating voltage, and may have a voltage regulator control circuit to select one of a plurality of power state profiles based at least in part on a classification of the workload, and to cause an update to a power state of the voltage regulator according to the selected power state profile. Other embodiments are described and claimed.

Abstract: In one embodiment, a processor includes: at least one core to execute a workload; a voltage regulator to provide an operating voltage to the at least one core; and a power controller coupled to the voltage regulator. The power controller may control the voltage regulator to provide the operating voltage, and may have a voltage regulator control circuit to select one of a plurality of power state profiles based at least in part on a classification of the workload, and to cause an update to a power state of the voltage regulator according to the selected power state profile. Other embodiments are described and claimed.

Abstract: In one embodiment, a processor includes: at least one core to execute a workload; a voltage regulator to provide an operating voltage to the at least one core; and a power controller coupled to the voltage regulator. The power controller may control the voltage regulator to provide the operating voltage, and may have a voltage regulator control circuit to select one of a plurality of power state profiles based at least in part on a classification of the workload, and to cause an update to a power state of the voltage regulator according to the selected power state profile. Other embodiments are described and claimed.

Abstract: Described is an apparatus which comprises: a first voltage regulator (VR) having a reference input node; and a first multiplexer to provide a reference voltage to the reference input node and operable to select one of at least two different reference voltages as the reference voltage.

Abstract: Described is an apparatus which comprises: a first voltage regulator (VR) having a reference input node; and a first multiplexer to provide a reference voltage to the reference input node and operable to select one of at least two different reference voltages as the reference voltage.

Abstract: A computing device, system and method. The computing device includes a memory storing instructions, and a processing circuitry coupled to the memory. The processing circuitry is configured to execute the instructions to process a first control signal and a second control signal from respective first and second control pins of a computing platform. The processing circuitry is further to transition the computing platform, based on a combination of the first control signal and the second control signal and using at least one voltage pin on the platform, between a low power state and a retention power state without transitioning to an operational power state in between.

Abstract: A computing device, system and method. The computing device includes a memory storing instructions, and a processing circuitry coupled to the memory. The processing circuitry is configured to execute the instructions to process a first control signal and a second control signal from respective first and second control pins of a computing platform. The processing circuitry is further to transition the computing platform, based on a combination of the first control signal and the second control signal and using at least one voltage pin on the platform, between a low power state and a retention power state without transitioning to an operational power state in between.

Abstract: A method and apparatus (e.g., semiconductor device) for setting voltages (e.g., guardbands) using “in situ,” or on-die, silicon measurements are described. In one embodiment the semiconductor device comprises: a process monitor to measure silicon parameters of the semiconductor device; and a controller coupled to the process monitor to set a voltage for use on at least a portion of the semiconductor device based on silicon process monitor measurements.

Abstract: Described is an apparatus which comprises: a first voltage regulator (VR) having a reference input node; and a first multiplexer to provide a reference voltage to the reference input node and operable to select one of at least two different reference voltages as the reference voltage.

Abstract: The present disclosure is directed to logging random “chirps” of IoT devices and rebroadcasting these chirps to other devices on demand. An apparatus consistent with the present disclosure includes a transmitter to communicate with a network of wireless-communication-enabled devices. The apparatus also includes a receiver to detect communications transmitted from the wireless-communication-enabled device. Further, the apparatus includes control unit logic to tally the number of electrical signals emitted from each wireless-communication-enabled device. In addition, the apparatus includes memory to store the number of emitted electrical signals. The apparatus further includes a power unit electrically coupled to the transmitter, receiver, and memory.

Abstract: Described is an apparatus which comprises: a first voltage regulator (VR) having a reference input node; and a first multiplexer to provide a reference voltage to the reference input node and operable to select one of at least two different reference voltages as the reference voltage.

Abstract: Technologies for low-power display refresh standby include a computing device with a display such as an LCD panel. The computing device may include a system-on-a-chip (SoC) with a processor, I/O subsystem, display controller, and memory. When the computing device determines that a display image is static, the computing device enters a low-power display refresh standby mode, powering down unneeded components of the SoC such as processor cores, peripheral devices, and memory other than a dedicated display buffer. The display controller may access the dedicated display buffer via the I/O subsystem and output the image to the display. The computing device may power down the I/O subsystem and the dedicated display buffer when a display controller FIFO is full of image data, and periodically power on the I/O subsystem and display buffer to fill the display controller FIFO. Other embodiments are described and claimed.

Abstract: Various embodiments are generally directed to an apparatus, method and other techniques for determining a sleep configuration state for each of a plurality of subsystems having an associated subsystem sleep control register for entry into a lower power state, configuring each of the associated subsystem sleep control registers with the sleep configuration state for each of the subsystems and enabling the sleep configuration state for each of the subsystems in parallel when transitioning to the lower power state.

Abstract: A method and apparatus (e.g., semiconductor device) for setting voltages (e.g., guardbands) using “in situ,” or on-die, silicon measurements are described. In one embodiment the semiconductor device comprises: a process monitor to measure silicon parameters of the semiconductor device; and a controller coupled to the process monitor to set a voltage for use on at least a portion of the semiconductor device based on silicon process monitor measurements.

Abstract: Technologies for low-power display refresh standby include a computing device with a display such as an LCD panel. The computing device may include a system-on-a-chip (SoC) with a processor, I/O subsystem, display controller, and memory. When the computing device determines that a display image is static, the computing device enters a low-power display refresh standby mode, powering down unneeded components of the SoC such as processor cores, peripheral devices, and memory other than a dedicated display buffer. The display controller may access the dedicated display buffer via the I/O subsystem and output the image to the display. The computing device may power down the I/O subsystem and the dedicated display buffer when a display controller FIFO is full of image data, and periodically power on the I/O subsystem and display buffer to fill the display controller FIFO. Other embodiments are described and claimed.

Abstract: Techniques and mechanisms to manage power states for a system-on-chip (SOC). Multiple modules of the SOC include a first module to perform a task including one or more accesses to a memory. In an embodiment, the SOC is transitioned to one of a path-to-memory-available (PMA) power state and a path-to-memory-not-available (PMNA) power state, where the transition is in response to an indication that, of the multiple modules, only the first module is to access the memory during the task. The PMA power state enables data communication between the memory and the first module and prevents data communication between the memory and any other module of the multiple modules. In another embodiment, the PMNA power state prevents data communication between the memory and any of the multiple modules, but allows a low latency transition from the PMNA power state to the PMA power state.

Abstract: The present application is directed to device federation. Interaction between devices in a federation may be conducted using reduced security, while interactions with devices outside the federation may be conducted with a variable security up to a standard level of security that may be associated with a communication protocol. A device may comprise at least a communication module and a federation module. The federation module may include at least a relationship rules module having at least one rule based on relationships between devices and a link security control module to control the amount of security utilized during interaction based on the at least one rule. The link security control module may also control how a device may be inducted into a federation by, if necessary, providing qualification data to qualify the device for induction.

Abstract: Described is an apparatus which comprises: a first voltage regulator (VR) having a reference input node; and a first multiplexer to provide a reference voltage to the reference input node and operable to select one of at least two different reference voltages as the reference voltage.