Patents by Inventor Vasudev Dasappa

Vasudev Dasappa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Built-in self test system and method
    Patent number: 7159145
    Abstract: External test equipment is used to simulate an internal BIST test, thus enabling the capture or generation of detailed test results. By simulating the BIST test sequence in real time during the test, the external tester may monitor an output from the BIST and determine the exact location of failures when they occur. The external tester may generate a bit fail map indicating whether each memory location passed or failed the BIST test.
    Type: Grant
    Filed: May 12, 2003
    Date of Patent: January 2, 2007
    Assignees: Infineon Technologies AG, International Business Machines Corporation
    Inventors: Li Wang, Vasudev Dasappa, Thomas Boehler
  • Built-in self test system and method
    Publication number: 20040230870
    Abstract: External test equipment is used to simulate an internal BIST test, thus enabling the capture or generation of detailed test results. By simulating the BIST test sequence in real time during the test, the external tester may monitor an output from the BIST and determine the exact location of failures when they occur. The external tester may generate a bit fail map indicating whether each memory location passed or failed the BIST test.
    Type: Application
    Filed: May 12, 2003
    Publication date: November 18, 2004
    Inventors: Li Wang, Vasudev Dasappa, Thomas Boehler