Patents by Inventor Vasudevan Srinivasan

Vasudevan Srinivasan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220244996
    Abstract: An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of cores; one or more peripheral component interconnects to couple the plurality of cores to memory, and in response to a core configuration command to deactivate a core of the plurality of cores, a region within the memory is updated with an indication of deactivation of the core.
    Type: Application
    Filed: April 11, 2022
    Publication date: August 4, 2022
    Inventors: Ankush VARMA, Nikhil GUPTA, Vasudevan SRINIVASAN, Krishnakanth SISTLA, Nilanjan PALIT, Abhinav KARHU, Eugene GORBATOV, Eliezer WEISSMANN
  • Patent number: 11341248
    Abstract: A system includes a processor coupled to an integrated circuit. The processor includes a non-volatile memory to store instructions to perform a boot process. The boot process is discontinued to prevent unauthorized use of the processor if a value received from the integrated circuit in response to a first value sent to the integrated is not valid.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: May 24, 2022
    Assignee: Intel Corporation
    Inventors: Haifeng Gong, Vasudevan Srinivasan, Antonio J. Hasbun Marin
  • Publication number: 20220129031
    Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.
    Type: Application
    Filed: November 5, 2021
    Publication date: April 28, 2022
    Inventors: Vasudevan Srinivasan, Krishnakanth V. Sistla, Corey D. Gough, Ian M. Steiner, Nikhil Gupta, Vivek Garg, Ankush Varma, Sujal A. Vora, David P. Lerner, Joseph M. Sullivan, Nagasubramanian Gurumoorthy, William J. Bowhill, Venkatesh Ramamurthy, Chris MacNamara, John J. Browne, Ripan Das
  • Patent number: 11301298
    Abstract: An apparatus and method for intelligently scheduling threads across a plurality of logical processors.
    Type: Grant
    Filed: March 28, 2020
    Date of Patent: April 12, 2022
    Assignee: INTEL CORPORATION
    Inventors: Ankush Varma, Nikhil Gupta, Vasudevan Srinivasan, Krishnakanth Sistla, Nilanjan Palit, Abhinav Karhu, Eugene Gorbatov, Eliezer Weissmann
  • Publication number: 20220100823
    Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) for software defined silicon security are disclosed. Example apparatus include a trusted agent determiner to (i) determine respective reputation scores associated with a plurality of agents in a mesh network, the plurality of agents associated with a plurality of semiconductor devices, respective ones of the semiconductor devices including circuitry configurable to provide one or more features, and (ii) select, based on the respective reputation scores, a first agent from the plurality of the agents to transmit a request to activate or deactivate at least one of the one or more features. Example apparatus also include an agent interface to, in response to the request, broadcast an activation or deactivation of the least one of the one or more features to the mesh network to cause the trusted agent determiner to update the reputation score of the first agent.
    Type: Application
    Filed: September 25, 2020
    Publication date: March 31, 2022
    Inventors: Katalin Klara Bartfai-Walcott, Arkadiusz Berent, Vasuki Chilukuri, Mark Baldwin, Vasudevan Srinivasan, Naresh Sehgal, David Novick, Bartosz Gotowalski
  • Publication number: 20220092154
    Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement and manage software defined silicon products are disclosed. Example semiconductor devices disclosed herein include circuitry configurable to provide one or more features. Disclosed example semiconductor devices also include a license processor to activate or deactivate at least one of the one or more features based on a license received via a network from a first remote enterprise system. Disclosed example semiconductor devices further include an analytics engine to report telemetry data associated with operation of the semiconductor device to at least one of the first remote enterprise system or a second remote enterprise system, the analytics engine to report the telemetry data in response to activation or deactivation of the at least one of the one or more features based on the license.
    Type: Application
    Filed: September 25, 2020
    Publication date: March 24, 2022
    Inventors: Katalin Klara Bartfai-Walcott, Arkadiusz Berent, Vasuki Chilukuri, Mark Baldwin, Vasudevan Srinivasan, Vinila Rose, Mariusz Oriol, Justyna Chilczuk, Bartosz Gotowalski
  • Patent number: 11169560
    Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: November 9, 2021
    Assignee: Intel Corporation
    Inventors: Vasudevan Srinivasan, Krishnakanth V. Sistla, Corey D. Gough, Ian M. Steiner, Nikhil Gupta, Vivek Garg, Ankush Varma, Sujal A. Vora, David P. Lerner, Joseph M. Sullivan, Nagasubramanian Gurumoorthy, William J. Bowhill, Venkatesh Ramamurthy, Chris Macnamara, John J. Browne, Ripan Das
  • Patent number: 11144085
    Abstract: An apparatus system is provided which comprises: a first component and a second component; a first circuitry to assign the first component to a first group of components, and to assign the second component to a second group of components; and a second circuitry to assign a first maximum frequency limit to the first group of components, and to assign a second maximum frequency limit to the second group of components, wherein the first component and the second component are to respectively operate in accordance with the first maximum frequency limit and the second maximum frequency limit.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: October 12, 2021
    Assignee: Intel Corporation
    Inventors: Asma H. Al-Rawi, Federico Ardanaz, Jonathan M. Eastep, Dorit Shapira, Krishnakanth Sistla, Nikhil Gupta, Vasudevan Srinivasan, Chris MacNamara
  • Patent number: 11137807
    Abstract: In one embodiment, a processor includes a non-volatile storage to store a plurality of configurations for the processor, the non-volatile storage including a plurality of entries to store configuration information for the processor for one of the plurality of configurations, the configuration information including at least one of a guaranteed operating frequency and a core count, at least one of the entries to store the core count. The processor further includes a power controller to control the processor to operate at one of the plurality of configurations based at least in part on a selected thermal set point of a plurality of thermal set points of the processor, each of the plurality of thermal set points associated with one of the configurations. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: October 5, 2021
    Assignee: Intel Corporation
    Inventors: Sandeep Ahuja, Nikhil Gupta, Vasudevan Srinivasan
  • Publication number: 20210303357
    Abstract: An apparatus and method for intelligently scheduling threads across a plurality of logical processors.
    Type: Application
    Filed: March 28, 2020
    Publication date: September 30, 2021
    Inventors: Ankush VARMA, Nikhil GUPTA, Vasudevan SRINIVASAN, Krishnakanth SISTLA, Nilanjan PALIT, Abhinav KARHU, Eugene GORBATOV, Eliezer WEISSMANN
  • Publication number: 20210103662
    Abstract: Methods and apparatus for restricted deployment of targeted processor firmware updates. During a patch enabling per-work flow, service entitlement license information comprising one of more service entitlements is generated and provisioned on one or more computing platforms. A restricted deployment microcode (uCode) update release (aka uCode patch) targeted for platforms having CPUs and/or XPUs with certain part identifier is sent to the one or more platforms. Run-time software and/or firmware on the platforms are executed to access the provisioned service entitlement license information, which is used to authentic and verify the restricted deployment uCode update release using a service entitlement having a part identifier associated with the platform's CPU. In one solution, authentication is performed using a hash-matching scheme and verification is used to verify the platform is properly licensed to load uCode included in the restricted deployment microcode (uCode) update release into the CPU.
    Type: Application
    Filed: December 18, 2020
    Publication date: April 8, 2021
    Inventors: Chinmay Ashok, Vasudevan Srinivasan, Atanas K. Iwanow, Martin G. Dixon, Scott J. Cape, Scott Bobholz, David T. Mayo, Vinila Rose, Lorie Wigle, Jason Kennedy
  • Publication number: 20210012445
    Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement software defined silicon feature licensing are disclosed. Example licensor systems disclosed herein includes a third party verifier to verify one or more credentials included in a request to become an authorized delegated licensor, the request received from a third party. Disclosed example licensor systems also include a feature identifier to identify a feature of a silicon structure which the third party is to be granted the authority to license.
    Type: Application
    Filed: September 25, 2020
    Publication date: January 14, 2021
    Inventors: Katalin Klara Bartfai-Walcott, Mark Baldwin, Arkadiusz Berent, Bartosz Gotowalski, Vasuki Chilukuri, Vasudevan Srinivasan, Justyna Chilczuk, Vinila Rose, Mariusz Oriol
  • Publication number: 20210011741
    Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to provide device enhancements for software defined silicon implementations are disclosed. Example apparatus disclosed herein include a request interface to receive a request for a timestamp. Disclosed example apparatus also include a property checker to determine a first value of an electrical property of a feature embedded in a silicon product, the feature having electrical properties that change over time. Disclosed example apparatus further include a relative time determiner to calculate a relative time between the request and a previous event based on the first value of the electrical property and a second value of the electrical property, the second value of the electrical property associated with the previous event.
    Type: Application
    Filed: September 25, 2020
    Publication date: January 14, 2021
    Inventors: Katalin Klara Bartfai-Walcott, Arkadiusz Berent, Vasuki Chilukuri, Mark Baldwin, Vasudevan Srinivasan, Bartosz Gotowalski
  • Publication number: 20210012357
    Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to protect against misuse of software defined silicon products are disclosed. Example semiconductor devices disclosed herein include circuitry configurable to provide one or more features. Disclosed example semiconductor devices also include a license processor determine whether first identification information associated with a license received via a network from an enterprise system corresponds to second identification information associated with at least one of the semiconductor device or a customer, and configure the circuitry to activate a first one of the one or more features specified in the license in response to the first identification information corresponding to the second identification information.
    Type: Application
    Filed: September 25, 2020
    Publication date: January 14, 2021
    Inventors: Katalin Klara Bartfai-Walcott, Arkadiusz Berent, Vasuki Chilukuri, Mark Baldwin, Vasudevan Srinivasan, Justyna Chilczuk, Bartosz Gotowalski
  • Patent number: 10856102
    Abstract: Embodiments are generally directed to sharing of environmental data for client device usage. An embodiment of a client device includes a processor; an environmental sensor to sense an environmental condition, an output of the sensor being a local environmental sensor value; and a wireless receiver to receive environmental data for a certain proximity area from a second client device according to an environmental data sharing protocol via a wireless network. The environmental data sharing protocol allows receipt of the environmental data without requiring pairing, bonding, or other relationship of client devices.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: December 1, 2020
    Assignee: Intel Corporation
    Inventors: Vasudevan Srinivasan, Barnes Cooper, Tawfik M Rahal-Arabi
  • Patent number: 10761579
    Abstract: In one embodiment, a system includes: a plurality of compute nodes to couple in a chassis; a first shared power supply to provide a baseline power level to the plurality of compute nodes; and an auxiliary power source to provide power to one or more of the plurality of compute nodes during operation at a higher power level than the baseline power level. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: September 1, 2020
    Assignee: Intel Corporation
    Inventors: Ankush Varma, Vasudevan Srinivasan, Eugene Gorbatov, Andrew D. Henroid, Barnes Cooper, David W. Browning, Guy M. Therien, Neil W. Songer, Krishnakanth V. Sistla, James G. Hermerding, II
  • Publication number: 20200225724
    Abstract: Examples herein relate to assigning, by a system agent of a central processing unit (CPU), an operating frequency to a core group based priority level of the core group while avoiding throttling of the system agent. Avoiding throttling of the system agent can include maintaining a minimum performance level of the system agent. A minimum performance level of the system agent can be based on a minimum operating frequency. Assigning, by a system agent of a central processing unit, an operating frequency to a core group based priority level of the core group while avoiding throttling of the system agent can avoid a thermal limit of the CPU. Avoiding thermal limit of the CPU can include adjusting the operating frequency to the core group to avoid performance indicators of the CPU. A performance indicator can indicate CPU utilization corresponds to Thermal Design Point (TDP).
    Type: Application
    Filed: March 27, 2020
    Publication date: July 16, 2020
    Inventors: Chris MACNAMARA, John J. BROWNE, Tomasz KANTECKI, David HUNT, Anatoly BURAKOV, Srihari MAKINENI, Nikhil GUPTA, Ankush VARMA, Dorit SHAPIRA, Vasudevan SRINIVASAN, Bryan T. BUTTERS, Shrikant M. SHAH
  • Publication number: 20200125389
    Abstract: Methods, apparatus, systems and machine-readable storage media of an edge computing device using an edge server CPU with dynamic deterministic scaling is disclosed. A processing circuitry arrangement includes processing circuitry with processor cores operating at a center base frequency and memory. The memory includes instructions configuring the processing circuitry to configure a first set of the processor cores of the CPU to switch the operating at the center base frequency to operating at a first modified base frequency, and a second set of the processor cores to switch the operating at the center base frequency to operating at a second modified base frequency. A same processor core within the first set or the second set can be configured to switch operating between the first modified base frequency or the second modified base frequency.
    Type: Application
    Filed: November 8, 2019
    Publication date: April 23, 2020
    Inventors: Stephen T. Palermo, Nikhil Gupta, Vasudevan Srinivasan, Christopher MacNamara, Sarita Maini, Abhishek Khade, Edwin Verplanke, Lokpraveen Mosur
  • Publication number: 20190384348
    Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.
    Type: Application
    Filed: February 24, 2017
    Publication date: December 19, 2019
    Inventors: Vasudevan SRINIVASAN, Krishnakanth V. SISTLA, Corey D. GOUGH, Ian M. STEINER, Nikhil GUPTA, Vivek GARG, Ankush VARMA, Sujal A. VORA, David P. LERNER, Joseph M. SULLIVAN, Nagasubramanian GURUMOORTHY, William J. BOWHILL, Venkatesh RAMAMURTHY, Chris MACNAMARA, John J. BROWNE, Ripan DAS
  • Publication number: 20190306654
    Abstract: Embodiments are generally directed to sharing of environmental data for client device usage. An embodiment of a client device includes a processor; an environmental sensor to sense an environmental condition, an output of the sensor being a local environmental sensor value; and a wireless receiver to receive environmental data for a certain proximity area from a second client device according to an environmental data sharing protocol via a wireless network. The environmental data sharing protocol allows receipt of the environmental data without requiring pairing, bonding, or other relationship of client devices.
    Type: Application
    Filed: June 20, 2019
    Publication date: October 3, 2019
    Inventors: Vasudevan Srinivasan, Barnes Cooper, Tawfik M Rahal-Arabi