Patents by Inventor Vasudevan Srinivasan
Vasudevan Srinivasan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240095315Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement license management solutions for software defined silicon (SDSi) products are disclosed. Example license management solutions disclosed herein include, but are not limited to, virtual resource migration using SDSi, resource configuration management using SDSi, hardware self-configuration using SDSi, reduced footprint agents using SDSi, performing SDSi usage evaluation and corresponding license transfer responsive to detected and/or predicted failures, transferring node locked SDSi licenses, transfer of SDSi licenses without a trusted license server, community license generation, expirable SDSi licenses via a reliable clock, non-node locked licenses via blockchain, and activating hardware features with a pre-generated hardware license.Type: ApplicationFiled: September 25, 2023Publication date: March 21, 2024Inventors: Katalin Bartfai-Walcott, Mariusz Oriol, Vasudevan Srinivasan, Peggy Irelan, Mariusz Stepka, Kaitlin Murphy, Bharat Pillilli, Mark Baldwin, Mateusz Bronk, Fariaz Karim, Arkadiusz Berent, Vasuki Chilukuri
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Publication number: 20240054039Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement software defined silicon feature configuration pay-as-you-go licensing are disclosed. A disclosed silicon semiconductor device includes a first counter that increments a first count when a timer expires and, responsive to expiration of the timer, a feature configuration sampler to sample a state of a configuration of a feature of the silicon semiconductor device. In addition, the silicon semiconductor device includes a second counter that increments a second count when the sampled state of the configuration of the feature indicates the feature is active. A feature up-time tracker is also included outputs a value representative of an amount of time the configuration has been active, where the amount of time is based on the first count and the second count.Type: ApplicationFiled: December 23, 2020Publication date: February 15, 2024Inventors: Vasudevan SRINIVASAN, Knut GRIMSRUD, Johan VAN DE GROENENDAAL, Mariusz ORIOL, Nishi AHUJA, Shen ZHOU, Samantha ALT, Katalin BARTFAI-WALCOTT, Arkadiusz BERENT
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Patent number: 11886918Abstract: An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of cores; one or more peripheral component interconnects to couple the plurality of cores to memory, and in response to a core configuration command to deactivate a core of the plurality of cores, a region within the memory is updated with an indication of deactivation of the core.Type: GrantFiled: April 11, 2022Date of Patent: January 30, 2024Assignee: INTEL CORPORATIONInventors: Ankush Varma, Nikhil Gupta, Vasudevan Srinivasan, Krishnakanth Sistla, Nilanjan Palit, Abhinav Karhu, Eugene Gorbatov, Eliezer Weissmann
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Publication number: 20230315143Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.Type: ApplicationFiled: June 5, 2023Publication date: October 5, 2023Inventors: Vasudevan Srinivasan, Krishnakanth V. Sistla, Corey D. Gough, Ian M. Steiner, Nikhil Gupta, Vivek Garg, Ankush Varma, Sujal A. Vora, David P. Lerner, Joseph M. Sullivan, Nagasubramanian Gurumoorthy, William J. Bowhill, Venkatesh Ramamurthy, Chris MacNamara, John J. Browne, Ripan Das
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Patent number: 11703906Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.Type: GrantFiled: November 5, 2021Date of Patent: July 18, 2023Assignee: Intel CorporationInventors: Vasudevan Srinivasan, Krishnakanth V. Sistla, Corey D. Gough, Ian M. Steiner, Nikhil Gupta, Vivek Garg, Ankush Varma, Sujal A. Vora, David P. Lerner, Joseph M. Sullivan, Nagasubramanian Gurumoorthy, William J. Bowhill, Venkatesh Ramamurthy, Chris MacNamara, John J. Browne, Ripan Das
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Publication number: 20230208731Abstract: Embodiments are generally directed apparatuses, methods, techniques and so forth determine an access level of operation based on an indication received via one or more network links from a pod management controller, and enable or disable a firmware update capability for a firmware device based on the access level of operation, the firmware update capability to change firmware for the firmware device. Embodiments may also include determining one or more configuration settings of a plurality of configuration settings to enable for configuration based on the access level of operation, and enable configuration of the one or more configuration settings.Type: ApplicationFiled: March 3, 2023Publication date: June 29, 2023Applicant: Intel CorporationInventors: MURUGASAMY K. NACHIMUTHU, MOHAN J. KUMAR, VASUDEVAN SRINIVASAN
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Patent number: 11650851Abstract: Methods, apparatus, systems and machine-readable storage media of an edge computing device using an edge server CPU with dynamic deterministic scaling is disclosed. A processing circuitry arrangement includes processing circuitry with processor cores operating at a center base frequency and memory. The memory includes instructions configuring the processing circuitry to configure a first set of the processor cores of the CPU to switch the operating at the center base frequency to operating at a first modified base frequency, and a second set of the processor cores to switch the operating at the center base frequency to operating at a second modified base frequency. A same processor core within the first set or the second set can be configured to switch operating between the first modified base frequency or the second modified base frequency.Type: GrantFiled: November 8, 2019Date of Patent: May 16, 2023Assignee: Intel CorporationInventors: Stephen T. Palermo, Nikhil Gupta, Vasudevan Srinivasan, Christopher MacNamara, Sarita Maini, Abhishek Khade, Edwin Verplanke, Lokpraveen Mosur
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Publication number: 20230132432Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to provide device enhancements for software defined silicon implementations are disclosed. Example non-transitory computer readable medium includes instructions to cause one or more processors to at least generate a first stock keeping unit, associate the first stock keeping unit with a semiconductor device, the first stock keeping unit associated with a first set of features to be provided by the semiconductor device, command the semiconductor device to activate a feature not included in the first set of features to cause the semiconductor device to provide a second set of features, generate a second stock keeping unit for the semiconductor device, and associate the second stock keeping unit with the semiconductor device and the second set of features to be provided by the semiconductor device.Type: ApplicationFiled: December 30, 2022Publication date: May 4, 2023Inventors: Katalin Klara Bartfai-Walcott, Arkadiusz Berent, Vasuki Chilukuri, Mark Baldwin, Vasudevan Srinivasan, Bartosz Gotowalski
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Patent number: 11599368Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to provide device enhancements for software defined silicon implementations are disclosed. Example apparatus disclosed herein include a request interface to receive a request for a timestamp. Disclosed example apparatus also include a property checker to determine a first value of an electrical property of a feature embedded in a silicon product, the feature having electrical properties that change over time. Disclosed example apparatus further include a relative time determiner to calculate a relative time between the request and a previous event based on the first value of the electrical property and a second value of the electrical property, the second value of the electrical property associated with the previous event.Type: GrantFiled: September 25, 2020Date of Patent: March 7, 2023Assignee: Intel CorporationInventors: Katalin Klara Bartfai-Walcott, Arkadiusz Berent, Vasuki Chilukuri, Mark Baldwin, Vasudevan Srinivasan, Bartosz Gotowalski
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Patent number: 11579897Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) for software defined silicon security are disclosed. Example apparatus include a trusted agent determiner to (i) determine respective reputation scores associated with a plurality of agents in a mesh network, the plurality of agents associated with a plurality of semiconductor devices, respective ones of the semiconductor devices including circuitry configurable to provide one or more features, and (ii) select, based on the respective reputation scores, a first agent from the plurality of the agents to transmit a request to activate or deactivate at least one of the one or more features. Example apparatus also include an agent interface to, in response to the request, broadcast an activation or deactivation of the least one of the one or more features to the mesh network to cause the trusted agent determiner to update the reputation score of the first agent.Type: GrantFiled: September 25, 2020Date of Patent: February 14, 2023Assignee: Intel CorporationInventors: Katalin Klara Bartfai-Walcott, Arkadiusz Berent, Vasuki Chilukuri, Mark Baldwin, Vasudevan Srinivasan, Naresh Sehgal, David Novick, Bartosz Gotowalski
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Patent number: 11573830Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement and manage software defined silicon products are disclosed. Example semiconductor devices disclosed herein include circuitry configurable to provide one or more features. Disclosed example semiconductor devices also include a license processor to activate or deactivate at least one of the one or more features based on a license received via a network from a first remote enterprise system. Disclosed example semiconductor devices further include an analytics engine to report telemetry data associated with operation of the semiconductor device to at least one of the first remote enterprise system or a second remote enterprise system, the analytics engine to report the telemetry data in response to activation or deactivation of the at least one of the one or more features based on the license.Type: GrantFiled: September 25, 2020Date of Patent: February 7, 2023Assignee: Intel CorporationInventors: Katalin Klara Bartfai-Walcott, Arkadiusz Berent, Vasuki Chilukuri, Mark Baldwin, Vasudevan Srinivasan, Vinila Rose, Mariusz Oriol, Justyna Chilczuk, Bartosz Gotowalski
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Patent number: 11567556Abstract: Examples herein relate to assigning, by a system agent of a central processing unit (CPU), an operating frequency to a core group based priority level of the core group while avoiding throttling of the system agent. Avoiding throttling of the system agent can include maintaining a minimum performance level of the system agent. A minimum performance level of the system agent can be based on a minimum operating frequency. Assigning, by a system agent of a central processing unit, an operating frequency to a core group based priority level of the core group while avoiding throttling of the system agent can avoid a thermal limit of the CPU. Avoiding thermal limit of the CPU can include adjusting the operating frequency to the core group to avoid performance indicators of the CPU. A performance indicator can indicate CPU utilization corresponds to Thermal Design Point (TDP).Type: GrantFiled: March 27, 2020Date of Patent: January 31, 2023Assignee: Intel CorporationInventors: Chris Macnamara, John J. Browne, Tomasz Kantecki, David Hunt, Anatoly Burakov, Srihari Makineni, Nikhil Gupta, Ankush Varma, Dorit Shapira, Vasudevan Srinivasan, Bryan T. Butters, Shrikant M. Shah
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Publication number: 20220413720Abstract: In an embodiment, a processor includes multiple processing engines and a power control unit. The power control unit is to receive a mapping of multiple virtual partitions to sets of the processing engines, and in response to a receipt of the mapping of multiple of virtual partitions: access a power limit table for the processor, and generate multiple virtual partition power limit tables based on the power limit table for the processor, where each virtual partition power limit table is associated with a different virtual partition. Other embodiments are described and claimed.Type: ApplicationFiled: June 25, 2021Publication date: December 29, 2022Inventors: Adwait Purandare, Ian Steiner, Vasudevan Srinivasan, Ankush Varma, Nikhil Gupta, Stanley Chen
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Publication number: 20220244996Abstract: An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of cores; one or more peripheral component interconnects to couple the plurality of cores to memory, and in response to a core configuration command to deactivate a core of the plurality of cores, a region within the memory is updated with an indication of deactivation of the core.Type: ApplicationFiled: April 11, 2022Publication date: August 4, 2022Inventors: Ankush VARMA, Nikhil GUPTA, Vasudevan SRINIVASAN, Krishnakanth SISTLA, Nilanjan PALIT, Abhinav KARHU, Eugene GORBATOV, Eliezer WEISSMANN
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Method and apparatus to prevent unauthorized operation of an integrated circuit in a computer system
Patent number: 11341248Abstract: A system includes a processor coupled to an integrated circuit. The processor includes a non-volatile memory to store instructions to perform a boot process. The boot process is discontinued to prevent unauthorized use of the processor if a value received from the integrated circuit in response to a first value sent to the integrated is not valid.Type: GrantFiled: December 21, 2018Date of Patent: May 24, 2022Assignee: Intel CorporationInventors: Haifeng Gong, Vasudevan Srinivasan, Antonio J. Hasbun Marin -
Publication number: 20220129031Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.Type: ApplicationFiled: November 5, 2021Publication date: April 28, 2022Inventors: Vasudevan Srinivasan, Krishnakanth V. Sistla, Corey D. Gough, Ian M. Steiner, Nikhil Gupta, Vivek Garg, Ankush Varma, Sujal A. Vora, David P. Lerner, Joseph M. Sullivan, Nagasubramanian Gurumoorthy, William J. Bowhill, Venkatesh Ramamurthy, Chris MacNamara, John J. Browne, Ripan Das
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Patent number: 11301298Abstract: An apparatus and method for intelligently scheduling threads across a plurality of logical processors.Type: GrantFiled: March 28, 2020Date of Patent: April 12, 2022Assignee: INTEL CORPORATIONInventors: Ankush Varma, Nikhil Gupta, Vasudevan Srinivasan, Krishnakanth Sistla, Nilanjan Palit, Abhinav Karhu, Eugene Gorbatov, Eliezer Weissmann
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Publication number: 20220100823Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) for software defined silicon security are disclosed. Example apparatus include a trusted agent determiner to (i) determine respective reputation scores associated with a plurality of agents in a mesh network, the plurality of agents associated with a plurality of semiconductor devices, respective ones of the semiconductor devices including circuitry configurable to provide one or more features, and (ii) select, based on the respective reputation scores, a first agent from the plurality of the agents to transmit a request to activate or deactivate at least one of the one or more features. Example apparatus also include an agent interface to, in response to the request, broadcast an activation or deactivation of the least one of the one or more features to the mesh network to cause the trusted agent determiner to update the reputation score of the first agent.Type: ApplicationFiled: September 25, 2020Publication date: March 31, 2022Inventors: Katalin Klara Bartfai-Walcott, Arkadiusz Berent, Vasuki Chilukuri, Mark Baldwin, Vasudevan Srinivasan, Naresh Sehgal, David Novick, Bartosz Gotowalski
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Publication number: 20220092154Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement and manage software defined silicon products are disclosed. Example semiconductor devices disclosed herein include circuitry configurable to provide one or more features. Disclosed example semiconductor devices also include a license processor to activate or deactivate at least one of the one or more features based on a license received via a network from a first remote enterprise system. Disclosed example semiconductor devices further include an analytics engine to report telemetry data associated with operation of the semiconductor device to at least one of the first remote enterprise system or a second remote enterprise system, the analytics engine to report the telemetry data in response to activation or deactivation of the at least one of the one or more features based on the license.Type: ApplicationFiled: September 25, 2020Publication date: March 24, 2022Inventors: Katalin Klara Bartfai-Walcott, Arkadiusz Berent, Vasuki Chilukuri, Mark Baldwin, Vasudevan Srinivasan, Vinila Rose, Mariusz Oriol, Justyna Chilczuk, Bartosz Gotowalski
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Patent number: 11169560Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.Type: GrantFiled: February 24, 2017Date of Patent: November 9, 2021Assignee: Intel CorporationInventors: Vasudevan Srinivasan, Krishnakanth V. Sistla, Corey D. Gough, Ian M. Steiner, Nikhil Gupta, Vivek Garg, Ankush Varma, Sujal A. Vora, David P. Lerner, Joseph M. Sullivan, Nagasubramanian Gurumoorthy, William J. Bowhill, Venkatesh Ramamurthy, Chris Macnamara, John J. Browne, Ripan Das