Abstract: A high-speed sample and hold phase detector for clock and data recovery systems is provided with a differentiating circuit coupled to a source of coded input data signals to provide bi-level differentiated output sampling pulses which are applied to a high-speed transformer. The output of the high-speed transformer is coupled to a high-speed fullwave diode bridge rectifying circuit whose output provides the error signal for the clock and data recovery circuit. The transformer is provided with a secondary winding having a center tap connected to a bi-level clock having clock signals whose rate is at twice the data rate. The D.C. error signal voltage amplitude is proportional to the phase difference between the clock signal connected to the center tap of the secondary winding of the transformer and the differentiated sampling pulses. The sampling pulses are employed to sample the clock signal which provides higher stability and enhances noise reduction.

Abstract: A compensated laser diode transmitter for high speed data transmission is provided with a pair of current switches, a novel current summing circuit and a novel current sink. The power output of the laser is sensed in real data time and employed to generate instantaneous feedback signals capable of instantaneously rebalancing and maintaining the power output of the laser diode.

Abstract: A coherent detection and decoding circuit coherently recovers data embedded in a self-clocking data signal by recovering the clock in one integrate and dump circuit and recovering the data in a second integrate and dump circuit. The two integrate and dump circuits are connected to the source of self-clocking data signal and to one of the outputs from a clock phase select switch which produces an inphase clock signal and a NOT inphase clock signal. The inphase clock signal is connected to the integrate and dump circuit which produces the output data signal and the NOT inphase clock signal is connected to the clock recovery integrate and dump circuit. When the presence of a data pulse is detected in the clock phase detection circuit the output signal is coupled to the clock phase select switch so as to reverse the output clock signals and synchronize the inphase clock signal with the data embedded in the self-clocking data input signal.

Abstract: A high speed, edge-triggered, set/reset flip-flop of relatively simple circuit configuration which operates on small, narrow pulses.

Abstract: Digital data is arranged into records for high density recording on a moving magnetic tape or other magnetic medium. A preamble and a postamble are formatted around a variable length data block to form a record for recording onto a movable magnetic medium. A unique character having a mirror image the same as the character is formatted after the preamble and before the postamble in order to allow recognition of the data when read in either forward or reverse direction. A flux change signal is always recorded in a ninth cell position of each character of the preamble, the postamble, the data and all other characters to be recorded, except in the ninth cell position of the unique character to insure a maximum of nine cell positions between successive clock signals and to permit immediate recognition of the end of a data block upon reading the unique character.