Abstract: Subject matter disclosed herein relates to arrangements and techniques that provide for identifying objects within an image such as the face position of a user of a portable electronic device. An application specific integrated circuit (ASIC) is configured to locate objects within images. The ASIC includes an image node configured to process an image and a search node configured to search the image for an object in the image. The ASIC also includes an ensemble node configured to confirm the presence of the object in the image. The ensemble node progressively compares, using computational engines that include accumulators, the pixel values of a template with pixel values of a region of interest in the image to create comparison result values.

Abstract: Subject matter disclosed herein relates to arrangements and techniques that provide for identifying objects within an image such as the face position of a user of a portable electronic device. An application specific integrated circuit (ASIC) is configured to locate objects within images. The ASIC includes an image node configured to process an image and a search node configured to search the image for an object in the image. The ASIC also includes an ensemble node configured to confirm the presence of the object in the image. The ensemble node compares the pixel values of a template with pixel values of a region of interest in the image to create comparison result values and normalize the comparison result values.

Abstract: Subject matter disclosed herein relates to arrangements and techniques that provide for identifying objects within an image such as the face position of a user of a portable electronic device. An application specific integrated circuit (ASIC) is configured to locate objects within images. The ASIC includes an image node configured to process an image and a search node configured to search the image for an object in the image. The search node includes an integral image generation unit configured to generate an integral image of the image and a Haar feature evaluation unit configured to evaluate search windows of the integral image with respect to Haar-like features. The ASIC also includes an ensemble node configured to confirm the presence of the object in the image.

Abstract: Subject matter disclosed herein relates to arrangements and techniques that provide for identifying objects within an image such as the face position of a user of a portable electronic device. An application specific integrated circuit (ASIC) is configured to locate objects within images. The ASIC includes an image node configured to process an image and a search node configured to search the image for an object in the image. The search node includes an integral image generation unit configured to generate an integral image of the image and a Haar feature evaluation unit configured to evaluate search windows of the integral image with respect to Haar-like features. The ASIC also includes an ensemble node configured to confirm the presence of the object in the image.

Abstract: Each of one or more temperature sensors of a computing system can measure and provide a temperature value (e.g., provide temperature data) to the system. In some embodiments, the system can apply an offset value, a time-based filter, and a weighting factor to each temperature value received from the one or more temperature sensors of the system. Based, at least in part, on the offsetting, filtering, and/or weighting, the computing system can determine (e.g., calculate, estimate, predict, etc.,) a temperature value representative of an enclosure temperature of the system. In some embodiments, based on the determined temperature value that is representative of the enclosure temperature, the computing system can perform appropriate subsequent processing in accordance with thermal management of the system.

Abstract: Systems and methods are disclosed for applying spatial filtering to raw image data. For example, a spatial filter may identify an n x n block of pixels from an image frame. The spatial filter has filter taps, each corresponding to one of the pixels of the n x n block. Pixel difference values between the input pixel and each of the neighboring pixels in the n x n block may be determined. Attenuation factors may be determined based on the pixel differences and brightness of the input pixel. Applying the attenuation factors to their respective filtering taps may produce attenuated filtering coefficients that are used to obtain filtered pixel values. By normalizing the sum of the filtered pixel values using the sum of the attenuated filtering coefficients, a spatially filtered output value corresponding to the current input pixel (e.g., located at the center of the n x n block) may be determined.

Abstract: Systems and methods are disclosed for applying spatial filtering to raw image data. In one embodiment, a spatial filter may identify an n×n block of pixels from the current image frame, the n×n block including a plurality of neighboring pixels being centered about a current input pixel and being of the same color component as the current input pixel. The spatial filter may include a plurality of filter taps, with one filter tap corresponding to each of the pixels within the n×n block. A set of filtering coefficients for each filter tap, which may be based on a Gaussian function, may be determined. A pixel difference value between the current input pixel and each of the plurality of neighboring pixels in the n×n block are determined, and the pixel differences may be used to determine an attenuation factor for each filter tap.

Abstract: Methods and apparatuses for computing an absolute difference of two vectors of numbers. In one aspect of the invention, a method for execution by a microprocessor in response to receiving a single instruction includes: receiving a first plurality of numbers and a second plurality of numbers; and generating simultaneously a third plurality of numbers, each of which is an absolute difference between a number in the first plurality of numbers and a number in the second plurality of numbers. The above operations are performed in response to the microprocessor receiving the single instruction.

Abstract: Methods and apparatuses for a data processing system are described herein. In one aspect of the invention, an exemplary apparatus includes a chip interconnect, a memory controller for controlling the host memory comprising DRAM memory, the memory controller coupled to the chip interconnect, a scalar processing unit coupled the chip interconnect wherein the scalar processing unit is capable of executing instructions to perform scalar data processing, a vector processing unit coupled the chip interconnect wherein the vector processing unit is capable of executing instructions to perform vector data processing, and an input/output (I/O) interface coupled to the chip interconnect wherein the I/O interface receives/transmits data from/to the scalar and/or vector processing units.

Abstract: At least one chip of a chipset in a computer system having at least one host processor and a host memory are described herein. In one aspect of the invention, an exemplary chip includes an interconnect, a memory interface coupled to the interconnect, the memory interface providing access to the host memory and controlling memory refresh and memory access, a host interface coupled to the interconnect, the host interface providing access to the host processor, and a programmable media processor coupled to the interconnect, the media processor accessing the host through the host interface and the media processor accessing the host memory through the memory interface, wherein the media processor processes time based media.