Abstract: A timing circuit for measuring time of arrival of an asynchronous event is disclosed. The timing circuit includes a counter, a register, a gray code-to-binary converter, and a cascade circuit. In response to a time of arrival of a trigger signal that denotes an occurrence of an asynchronous event, the counter generates a set of high-order binary bits and the register generates a set of gray code bits. The gray code-to-binary converter then converts the set of gray code bits to a set of low-order binary bits. Finally, the cascade circuit concatenates the high-order binary bits and the low-order binary bits to form the time of arrival of the asynchronous event.

Abstract: A timing circuit for measuring time of arrival of an asynchronous event is disclosed. The timing circuit includes a counter, a register, a gray code-to-binary converter, and a cascade circuit. In response to a time of arrival of a trigger signal that denotes an occurrence of an asynchronous event, the counter generates a set of high-order binary bits and the register generates a set of gray code bits. The gray code-to-binary converter then converts the set of gray code bits to a set of low-order binary bits. Finally, the cascade circuit concatenates the high-order binary bits and the low-order binary bits to form the time of arrival of the asynchronous event.