Abstract: Methods are provided for fabricating silicon carriers with conductive through-vias that allow high-yield manufacture of silicon carrier with low defect density. In particular, methods are provided which enable fabrication of silicon carries with via diameters such as 1 to 10 microns in diameter for a vertical thickness of less than 10 micrometers to greater than 300 micrometers, which are capable robust to thermal-mechanical stresses during production to significantly minimize the thermal mechanical movement at the via sidewall interface between the silicon, insulator, liner and conductor materials.

Abstract: Methods of making vertical profile FinFET gate electrodes via plating upon a thin gate dielectric are disclosed. In one embodiment, a method for forming a transistor, comprises: providing a semiconductor topography comprising a semiconductor substrate and a semiconductor fin structure extending above the substrate; forming a gate dielectric across exposed surfaces of the semiconductor topography; patterning a mask upon the semiconductor topography such that only a select portion of the gate dielectric is exposed that defines where a gate electrode is to be formed; and plating a metallic material upon the select portion of the gate dielectric to form a gate electrode across a portion of the fin structure.

Abstract: Silicide formation processes are disclosed that use an electrochemical displacement reaction in the absence of an externally applied current or potential. In an embodiment, a method for forming an integrated circuit comprises: depositing a metallic material upon select areas of a semiconductor topography comprising silicon by contacting the semiconductor topography with an aqueous solution comprising an acid and a metal salt to cause an electrochemical displacement reaction in the absence of an externally applied current or potential, wherein a concentration of the metal salt in the aqueous solution is about 0.01 millimolar to about 0.5 millimolar; and annealing the metallic material to form a silicide upon the areas of the semiconductor topography comprising the silicon.

Abstract: Methods are provided for fabricating silicon carriers with conductive through-vias that allow high-yield manufacture of silicon carrier with, low defect density. In particular, methods are provided which enable fabrication of silicon, carries with via diameters such as 1 to 10 microns in diameter for a vertical thickness of less than 10 micrometers to greater than 300 micrometers, which are capable robust to thermal-mechanical stresses during production to significantly minimize the thermal mechanical movement at the via sidewall interface between the silicon, insulator, liner and conductor materials.